Qualcomm Incorporated

Chia Heng Chang

Hadi Goudarzi

Li Hsiang Sun

Russell Deans

Behnam Amelifard

Zhi Zhu

Miao Li

Minhan Chen

Deqiang Song

Chad Everett Winemiller

Yu Song

Kenneth Arcudia

Jon Boyette

Kevin Wayne Spears

Clock-data timing in a multi-lane serial data communication link may be adjusted to compensate for drift. A reference lane may be selected and periodically trained to adjust clock-data timing. In response to initiation of a first lane transitioning from an active state to an inactive state, first information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. Then, in response to initiation of the first lane transitioning back from the inactive state to the active state, second information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. The clock-data timing of the first lane may be adjusted based on the first information and the second information.

System and method for adjusting clock-data timing in a multi-lane data communication link

A receiver is provided that generates a data sampling clock that is offset by clock offset that is a function of a decision feedback equalizer gain to account for a data sampling timing error that would occur without the clock delay.

Receiver with cancellation of intrinsic offset from decision feedback equalization to enhance data margin

Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

Clock data recovery with non-uniform clock tracking

Aspects disclosed in the detailed description include apparatuses, methods, and systems for glitch-free clock switching. In this regard, in one aspect, an electronic circuit is switched from a lower-frequency reference clock to a higher-frequency reference clock. An oscillation detection logic is configured to determine the stability of the higher-frequency reference clock prior to switching the electronic circuit to the higher-frequency reference clock. The oscillation detection logic derives a sampled clock signal from the higher-frequency reference clock, wherein the sampled clock signal has a slower frequency than the lower-frequency reference clock. The oscillation detection logic then compares the sampled clock signal against the lower-frequency reference clock to determine the stability of the higher-frequency reference clock. By deterministically detecting stability of a reference clock prior to switching to the reference clock, it is possible to avoid premature switching to an unstable reference clock, thus providing glitch-free clock switching in the electronic circuit.

Apparatuses, methods, and systems for glitch-free clock switching

A code converter is provided. The code converter includes a plurality of serial shift registers arranged to convert an input to a thermometer output. The code converter further includes a plurality of clock control circuits each configured to provide a clock to a corresponding one of the shift registers. A method of generating a signal in thermometer code is provided. The method includes enabling a subset of a plurality of shift registers and converting an input to a thermometer output by the plurality of shift registers. Another code converter is further provided. The code converter includes means for converting an input to a thermometer output. The means for converting includes a plurality of shift registers. The code converter further includes means for enabling a subset of the shift registers.

Thermometer code converter

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San Diego, CA, United States of America

Chia Heng Chang