Silicon Integrated Systems Corporation

Chia-hao Yang

Tze-hsiang Chao

Chia-jung Liu

The present invention provides a way of hysteretic switching for efficiently reducing the heavy switching between two adjacent coarse intervals. The present invention disposes a number of fine intervals to cover a range which is larger than the length of one coarse interval. Each coarse interval comprises some extra fine intervals which are exceeded the boundary of the coarse intervals in one side. The heavy switching will be postponed until the extra fine intervals are used up. In the meantime, the fine calibration unit records the number of extra fine interval which be used. An extra-boundary value will be recorded in the fine calibration unit for determining an initial fine interval in another coarse interval if the heavy switching occurs. It should be noted that the extra-boundary value could be a positive or minus value corresponding to which a forward coarse interval or a backward coarse interval the reference signal drifts into. The present invention also provides a method for reducing heavy switching between two coarse intervals. It is obvious that the probability of the heavy switching occurring will be efficiently decreased by the way of hysteretic switching of the present invention. Furthermore, the mismatch and noises due to the heavy switching between the coarse intervals can be effectively diminished.

Apparatus and method of switching intervals

A system for clock-switching applied in the field of integrated circuits is described. A phase interpolator converts an input clock signal into a clock_A and a clock_B having a phase difference therebetween and transmitting the clock_A and the clock_B. A switch command unit connected to the phase interpolator receives either the clock_A or the clock_B serving as a triggering signal for triggering the switch command unit to transform an input switching signal into an output switching signal when the output switching signal is located in either a rising or a falling edge. A selecting device connected to the phase interpolator and the switch command unit, selects either clock_A or clock_B according to the output switching signal from the switch command unit to output a clock-switching signal composed of clock_A and clock_B.

System and method for clock switching

An apparatus and a method of controlling and tuning clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of fixed phase intervals therebetween. At least one of the fixed phase intervals is equal to complete 360 degrees which are divided by the number of the output signals to cover the phase range of complete 360 degrees. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal. The phase detector connected to the first fine calibration unit is used to detect a phase difference between the reference and the feedback signals and outputting an indicating signal corresponding to the phase difference between the reference and the feedback signals. The controller controls the coarse calibration unit and the first fine calibration unit to align the feedback signal to the reference signal according to the indicating signal generated from the phase detector. The rotating detector rapidly tunes the phase difference between the feedback signal and the reference signal by adding a number of time delays to the feedback signal when the feedback signal and the reference signal are miss-aligned.

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Douliou, Taiwan

Chia-hao Yang