Semiconductor Manufacturing International (shanghai) Corporation

Chia Hao Lee

Hanming Wu

John Chen

An apparatus for implanting ions of a selected species into a semiconductor wafer includes an ion source, an accelerator, and an magnetic structure. The ion source is configured to generate an ion beam. The accelerator is configured to accelerate the ion beam, where the accelerated ion beam includes at least a first portion having a first energy and a second portion having a second energy. The magnetic structure is configured to deflect the first portion of the accelerated ion beam in a first path trajectory and the second portion of the accelerated ion beam in a second path trajectory. The first and second path trajectories have a same incident angle relative to a surface region of the semiconductor wafer.

Method for dual energy implantation for ultra-shallow junction formation of MOS devices

A method for forming a lightly doped drain (LDD) region in a semiconductor substrate. The method includes generating an ion beam of a selected species, and accelerating the ion beam, wherein the accelerated ion beam includes a first accelerated portion and a second accelerated portion. The method further includes deflecting the accelerating ion beam, wherein the first and second accelerated portions are concurrently deflected into a first path trajectory having a first deflected angle and second path trajectory having a second deflected angle. In an embodiment, the first and second path trajectories travel in the same direction, which is perpendicular to the surface region of the semiconductor wafer, and the first deflected angle is greater than the second deflected angle. In an embodiment, the selected species may include an n-type ion comprising phosphorous (P), arsenic (As), or antimony (Sb).

A method for forming a MOS device with an ultra shallow lightly doped diffusion region includes providing a gate dielectric layer overlying a substrate surface region, forming a gate structure overlying the gate dielectric layer, performing a first implant process using a germanium species to form an amorphous region within an LDD region using the gate structure as a mask, and performing a second implant process in the LDD region using a P-type impurity and a carbon species. A first thermal process activates the P-type impurity in the LDD region, forming side wall spacers overlying the gate structure, and performing a third implant process using a first impurity to form active source/drain regions in a vicinity of the surface region adjacent to the gate structure using the gate structure and the spacers as a mask. A second thermal process then activates the first impurity in the active source/drain regions.

Method for forming P-type lightly doped drain region using germanium pre-amorphous treatment

A method for manufacturing a MOS device. The method includes providing a semiconductor substrate. The method forms a gate dielectric layer overlying the semiconductor substrate and a polysilicon gate overlying the gate dielectric layer. The polysilicon gate is characterized by a thickness, a width and a polysilicon footing profile. In a specific embodiment, the method performs a TCAD simulation and determines a response of device performance due to the polysilicon footing profile from the model. The method uses the model to provide a process control window for fabricating the polysilicon gate.

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Shanghai, China

Chia Hao Lee