Taiwan Semiconductor Manufacturing Comp. Ltd.

Anpec Electronics Corporation

Microjet Technology Company, Ltd.

Wistron Neweb Corporation

Realtek Semiconductor Inc.

Industrial Technology Research Institute

Delta Electronics, Inc.

Institute of Nuclear Energy Research

Mediatek Corporation

Au Optronics Corporation

Young Lighting Technology Corporation

Apple Inc.

Phison Electronics Corporation

Unimicron Technology Corporation

Taiwan Semiconductor Manufacturing Co., Ltd.

Chia-Hao Chang

Chih-Hao Wang

Yu-Ming Lin

Lin-Yu Huang

Jia-Chuan You

Cheng-Chi Chuang

Li-Zhen Yu

Tien-Lu Lin

Wai-Yi Lien

Kuan-Lun Cheng

Sheng-Tsung Wang

Yung-Fa Lin

Chun-Hsiung Lin

Shih-Chuan Chiu

Chi-Feng Huang

Yung-Lung Han

Shih-Chang Chen

Chun-Yuan Chen

Wei-Ming Lee

Shou-Yi Hsu

Meng-Wei Wu

Jia-Yu Liao

Ying-Lun Chang

Hung-Hsin Liao

Che-Wei Huang

Shou-Hung Chen

Jheng-Wei Chen

Kuo-Cheng Chiang

Huan-Chieh Su

Wei-Hao Wu

Carlos H Diaz

Ying-Keung Leung

Chung-Cheng Wu

Yi-Hsiung Lin

Chih-Chao Chou

Chun-Chieh Chan

Pei-Yu Wang

Jean-Pierre Colinge

Zhi-Chang Lin

Cheng-Long Chen

Ching-Wei Tsai

Chia-Wei Chen

Ru-Gun Liu

Chih-Ming Lai

Jiann-Tyng Tzeng

Chi-Wen Liu

Chih-Liang Chen

Shi Ning Ju

Charles Chew-Yuen Young

Tai-Lai Tung

Yi-Cheng Chen

Pei-Hsun Wang

Chin-Lung Lin

Ko-Yin Lai

Ching-Wen Chen

Lei-Chun Chou

Gwan-Sin Chang

Kuo-Cheng Ching

Hai-Ching Chen

Han-Jong Chia

Bo-Feng Young

Hsin-Yen Huang

Kai-Wen Cheng

Chi-Lin Teng

Kuan-lun Cheng

Guan-Lin Chen

Jung-Chien Cheng

Ting-Ya Lo

Chun-Hung Liao

Shih-Hsien Tseng

Chi-Chih Chen

Pinyen Lin

Sung-Li Wang

Kuan-Ting Pan

Shin-Yi Yang

Shi-Ning Ju

Chih-Ming Wang

Chien-Chih Chen

Huang-Lin Chao

Yu Cheng Chen

Shuen-Shin Liang

Chia-Hung Chu

Prashant Mandlik

Yueh-Lung Huang

Kai-Ming Yang

Hsin-Hsin Shen

Shih-Chieh Liao

Shih-Wei Wang

Po-Chin Chang

Li-Pang Mo

Hung-Yi Huang

Kuo-cheng Chiang

Chih-Hsien Hsu

Meei-Ling Jan

Fu-Ching Tung

Chung-Hung Chen

Jin-Ming Chen

Muh-Wang Liang

A semiconductor structure includes a first epitaxial source/drain (S/D) feature disposed over a first semiconductor fin, a second epitaxial S/D feature disposed over a second semiconductor fin and adjacent to the first epitaxial S/D feature, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, and a conductive feature disposed in the ILD layer and electrically coupled to the first epitaxial S/D feature and the second epitaxial S/D feature. The conductive feature includes first portions having bottom surfaces contacting the first and the second epitaxial S/D features, and a second portion having a bottom surface contacting the ILD layer. The bottom surface of the second portion is above the bottom surface of the first portions.

Methods of forming source/drain contacts in field-effect transistors

The present disclosure describes a method for forming an interconnect structure. The method can include forming a first layer of insulating material on a substrate, forming a via recess within the layer of insulating material, filling the via recess with a layer of conductive material, selectively growing a second layer of insulating material over the first layer of insulating material, and opening the second layer of insulating material to the layer of conductive material while growing the second layer of insulating material.

Isolation structure for metal interconnect

A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.

Gate isolation structure

Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

Low parasitic capacitance contact structure

A semiconductor structure includes first and second epitaxial features, at least one semiconductor channel layer connecting the first and second epitaxial features, and a gate structure engaging the semiconductor channel layer. The first and second epitaxial features, the semiconductor channel layer, and the gate structure are at a frontside of the semiconductor structure. The semiconductor structure also includes a backside metal wiring layer at a backside of the semiconductor structure, and a backside conductive contact electrically connecting the first epitaxial feature to the backside metal wiring layer. The backside metal wiring layer is spaced away from the gate structure with an air gap therebetween.

Semiconductor device with air gaps and method of fabrication thereof

Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.

Semiconductor devices including low-k metal gate isolation and methods of fabrication thereof

The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.

Semiconductor structure with a laminated layer

A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Dual side contact structures for source/drain regions in semiconductor transistor devices and method of forming

Provided are devices with conductive contacts and methods for forming such devices. A method includes forming a lower conductive contact in a dielectric material and over a structure, wherein the lower conductive contact has opposite sidewalls that extend to and terminate at a top surface. The method also includes separating an upper portion of each sidewall from the dielectric material and locating a barrier material between the upper portion of each sidewall and the dielectric material. Further, the method includes forming an upper conductive contact over the lower conductive contact.

Conductive structure interconnects with downward projections

A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Source/drain metal contact and formation thereof

A clock control method for a High Definition Multimedia Interface (HDMI) receiver operating in a power-saving mode in a sink device is provided. The HDMI receiver has a first module, a second module, and a third module. The clock control method includes the following stages. A clock signal is enabled to be sent to the first module and the third module during a first region of received data. The clock signal is disabled to be sent to the second module during the first region of the received data. The clock signal is enabled to be sent to the third module and the clock signal is disabled to be sent to the first module and the second module during a second region of the received data.

Clock control method and electronic device thereof

A method includes a gate electrode, a first spacer, a second spacer, a metal cap, and a dielectric structure. The gate electrode is over a substrate. The first spacer structure extends along a first sidewall of the gate electrode. The second spacer structure extends along a second sidewall of the gate electrode. The metal cap is over the gate electrode. The dielectric structure is over the gate electrode, the first spacer structure, and the second spacer structure. The dielectric structure has a top segment higher than a top segment of the metal cap.

Semiconductor device with metal cap on gate

A semiconductor device includes a semiconductor substrate, a gate electrode, a source/drain contact, a conductive structure, and a dielectric liner. The semiconductor substrate has a channel region and a source/drain region. The gate electrode is over the channel region. The source/drain contact is over the source/drain region. The conductive structure is over a top surface of the source/drain contact. The dielectric liner surrounds the conductive structure and is over the top surface of the source/drain contact.

Semiconductor device

A method for etching a tungsten silicide (WSix) layer during formation of a gate electrode in an integrated circuit is disclosed. The method uses an etchant gas comprising nitrogen gas (N) and oxygen gas (O) in a specified flow ratio. The etchant gas may also comprise chlorine gas (Cl) and tetrafluoromethane (CF). The selectivity of the etchant gas containing Ofor WSix versus polysilicon is much higher, which reduces overetching and provides more control in methods for producing a gate electrode. A gate electrode produced by such a method is also disclosed.

Etching methods for integrated circuits

Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure.

Semiconductor device having backside via and method of fabricating thereof

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Hsinchu, Taiwan

Chia-Hao Chang