United Microelectronics Corp.

Lite-on Technology Corporation

Lite-on Electronics (guangzhou) Co., Ltd.

Chia-Fu Yeh

Chun-Lung Chen

Chiou-Chu Lai

Chien-Chu Chen

Hsi-Mao Hsiao

Wen-Sheng Chien

Ming-Yao Cheng

Wen-Shan Wei

Yu-Chang Chow

W H Cheng

Jui-Chun Kuo

Cobby Lee

Chia-Tse Liang

C M Chi

Jung-Huang Chen

A battery cell balancing control system and a battery management method thereof are disclosed. The battery cell balancing control system is used for managing a battery apparatus, wherein the battery apparatus has a plurality of battery cells. The battery cell balancing control system comprises a detection module, a battery management module, and an adjusting module. The detection module is used for executing a battery checking procedure on the plurality of battery cells to generate a detection result. The battery management module is used for determining whether the plurality of battery cells has a controlled cell according to the detection result. If the controlled cell has not been found among the plurality of battery cells, the battery management module controls the adjusting module to execute a battery cell balancing procedure until the controlled cell is found.

Battery cell balancing control system and battery management method thereof

A method for inspecting a pattern defect process is disclosed, in which a layer is formed to raise a signal-to-noise ratio on the substrate. This invention also provides a method for inspecting a pattern defect process. First of all, a substrate is provided. Then, a device profile is formed on the substrate, wherein the device profile comprises a defect portion. Then, a layer is formed on the device profile and the substrate, wherein the layer has an etch selectivity different from the etch selectivity of the device profile. Next, the layer is removed partially to stop on the device profile and to cause a revere mask. Then, the device profile is etched on the substrate by using the revere mask as a mask. Finally, the revere mask is removed.

Method for inspecting a pattern defect process

In accordance with the present invention, a method is provided for dry cleaning a processing chamber. This method comprises the step of introducing a first cleaning process gas into the processing chamber. A plasma is formed from the first cleaning process gas and maintained for a first time period. Next, repeating the step of introducing the cleaning process gas, a second cleaning process gas is introduced into the processing chamber and maintained the plasma for a second time period. As a result, the present invention is capable of removing polymer built up on the processing chamber's interior surfaces to achieve a high yield and maintaining throughput of the substrates in the plasma processing system.

Method for dry cleaning metal etching chamber

A process for cleaning the interior walls of a reaction chamber after a number of silicon wafers is etched inside the chamber. The cleaning process includes bombarding the interior walls of the chamber with a first type of plasma in a dry cleaning operation, and then bombarding the interior walls of the chamber with a second type of plasma containing the element hydrogen in a warm-up operation. No silicon wafers need to be placed inside the chamber when the dry cleaning operation or the warm-up operation is conducted.

Method for cleaning interior of etching chamber

A semiconductor wafer has a substrate, a first region in the substrate that is used for a logic circuit, and a second region in the substrate that is used for a memory cell. A first gate in the first region and a second gate in the second region are simultaneously formed on the substrate. The first gate and the second gate both include a gate dielectric layer, a polysilicon layer, a tungsten silicide layer and a cap layer, in ascending order. The cap layer and the tungsten silicide layer are then removed from the first gate. A spacer around each gate is then formed. This completes the second type MOS transistor in the memory cell of DRAM. A titanium silicide layer on the surface of the substrate adjacent to the first gate and on the surface of the polysilicon layer of the first gate is formed so as to complete the formation of the first type MOS transistor.

Method for forming different types of MOS transistors on a semiconductor wafer

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Taipei, Taiwan

Chia-Fu Yeh