Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Fu Lin

Yen-Ming Chen

Hsin-Hui Lee

Kai-Ming Ching

Chao-Yuan Su

Li-Chih Chen

Wen-Hsiang Tseng

Wen-Chang Kuo

Ta-Min Lin

Shun-Liang Hsu

Cheng-Yu Chu

Szu-Yao Wang

Yue-Ying Jian

Li-Chi Chen

Sheng-Liang Pan

Yang-Tung Fan

Li-Chen Chen

Hao-Chih Tien

Kai-Ming Chin

Yeng-Ming Chen

Hong-Wen Huang

Kuo-Ching Lee

Chia-Tsun Hsu

A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.

Method to improve bump reliability for flip chip device

A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CFand SF, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.

Fluxless bumping process

A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.

Application of impressed-current cathodic protection to prevent metal corrosion and oxidation

A method for protecting a semiconductor process wafer surface from contacting thermally degraded photoresist including providing a semiconductor process wafer having a process surface; forming a protective layer over selected areas of the process surface said protective layer including a resinous organic material having a glass transition temperature (Tg) that is about greater than a thermal treatment temperature; forming a photoresist layer over at least a portion of the protective layer to include a photolithographic patterning process; and subjecting the semiconductor process wafer to the thermal treatment temperature.

Method of forming a solder ball using a thermally stable resinous protective layer

A flush system comprising a network of conduits, valves and screens that can be interposed between the process container and solvent re-claim tank components of a dry film photoresist (DFR) remover system, for example, that is used in the processing and packaging of integrated circuit chips. By operation of the valves in the flush system, DFR particles can be removed from the DFR remover system in order to prevent or minimize particle clogging of a particle filter in the DFR remover system. The screens in the flush system can be periodically cleaned by reverse flow of solvent or by operation of a nitrogen and DI (deionized) water purge system.

Flush system for dry film photoresist remover

A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF , SF , and H and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.

Fluxless bumping process using ions

A stencil design for solder paste printing, or other metal stencil printing, is disclosed. A stencil for stencil printing of solder onto a semiconductor wafer for semiconductor wafer bumping includes a substrate. The substrate has a hole defined therein substantially shaped to correspond to and receptive to the semiconductor wafer. An interior edge of the substrate surrounds the hole, and has an upper lip under which the semiconductor wafer is positioned. The upper lip of the interior edge of the substrate surrounding the hole substantially prevents the solder from flowing onto sides and a bottom of the semiconductor wafer during stencil printing of the solder. The cross-profile shape of the upper lip may in one embodiment be rectangular, whereas in another embodiment be triangular.

Stencil design for solder paste printing

A Ferris wheel-like stripping or cleaning mechanism that can be used in semiconductor fabrication, such as in photoresist or other stripping, or wafer or other cleaning, is disclosed. A stripping mechanism can include a container to hold a chemical, such as a photoresist stripping chemical, a wafer cleaning chemical, or another type of chemical. The mechanism can also include a component to move semiconductor wafers through the chemical in the container in a Ferris wheel-like motion. The component may include wafer holders for the wafers that are swivably mounted about an axis of rotation. As the one or more wafer holders rotate about the axis of rotation through the chemical in the container, the wafer holders remain in a substantially constant vertical and horizontal orientation.

Ferris wheel-like stripping or cleaning mechanism for semiconductor fabrication

Within a method for fabricating a microelectronic, and a microelectronic fabrication fabricated in accord with the method, there is formed upon a bond pad formed over a substrate a conductor passivation layer. Within the method and the microelectronic fabrication, the bond pad is formed from a conductor material selected from the group consisting of aluminum and aluminum alloy conductor materials, and the conductor passivation layer is formed from a noble metal conductor material. The invention provides particular value for fabricating color filter sensor image array optoelectronic microelectronic fabrications with attenuated bond pad corrosion.

Microelectronic fabrication with corrosion inhibited bond pad

A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the Created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.

Method for improving bump reliability for flip chip devices

A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the act of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. An electrically conductive redistribution trace is deposited over the under bump metallurgy. A photoresist layer is deposited, patterned and developed to provide portions selectively protecting the electrically conductive redistribution trace and the under bump metallurgy. Excess portions of the electrically conductive redistribution trace and under bump metallurgy not protected by the photoresist are removed.

Method of making a wafer level chip scale package

A DFR laminating and PET removing system which is capable of both laminating a dry film resist (DFR) layer on a semiconductor wafer and removing a DFR support film such as polyethylene terepthalate (PET) from the DFR layer on the wafer at a single location. The DFR laminating and PET removing system of the present invention comprises a PET support film removing head for removing a portion of PET film from the semiconductor wafer substrate after the PET film portion and dry film resist (DFR) portion are laminated from a DFR tape onto the wafer and before the DFR portion is cut from the DFR tape.

DFR laminating and film removing system

A method of forming reflowed bumps comprising the following sequential steps. A wafer is provided. A series of spaced initial bumps is formed upon the wafer. The initial bumps having exposed side walls and top surfaces and organic residue over the initial bump side walls and/or the initial bump top surfaces. The organic residue is simultaneously removed from the initial bump side walls and top surfaces with the forming a surface oxide layer over the initial bump side walls and top surfaces. The surface oxide layer is stripped from the initial bump top surfaces and an upper portion of the initial bump side walls to form partially exposed bumps. The partially exposed bumps are heat treated to melt the partially exposed bumps to form the reflowed bumps.

Bump reflow method by inert gas plasma

A method including the acts of providing a semiconductor device having a plurality of misalignment ruler markers formed therein for measuring removable layer opening misalignment in the X and Y directions, a bond pad and the passivation layer with an opening therein down to the bond pad. A removable layer is formed over the semiconductor device and includes an opening therein down to the bond pad. Preferably this action includes depositing, patterning and developing a dry photoresist film layer over the semiconductor device with an opening therein down to the bond pad. The next act includes measuring the misalignment of the opening in the passivation layer by counting the number of misalignment ruler markers visibly exposed by the opening in the X-direction and also the Y-direction.

Growing community of inventors

Hsin-Chu, Taiwan

Chia-Fu Lin