Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Fu Lee

Yu-Der Chih

Yi-Chun Shih

Hon-Jarn Lin

Po-Hao Lee

Ku-Feng Lin

Yue-Der Chih

Yen-An Chang

Shih-Lien Linus Lu

Jonathan Tsung-Yung Chang

Wen-Ting Chu

Chung-Cheng Chou

Chih-Yang Chang

Kai-Chun Lin

Chien-Yin Liu

Kuan-Chun Chen

Hsueh-Chih Yang

Yu-Lin Chen

Hidehiro Fujiwara

Tien-Chun Yang

Hung-Chang Yu

Fang-Shi Jordan Lai

Yuan-Long Siao

Chieh-Pu Lo

Wesley Lin

Caleb Yu-Sheng Cho

Chih-Feng Li

Jhon-Jhy Liaw

Yen-Huei Chen

Ping-Wei Wang

Tsung-Lin Lee

Chang-Yun Chang

Kuo-Ching Huang

Yu-Wei Ting

Chun-Yang Tsai

Gu-Huan Li

Zheng-Jun Lin

Tien-Chung Yang

Meng-Chun Shih

Ching-Huang Wang

Wei-Chang Zhao

Haruki Mori

Chin-I Su

Tang-Xuan Zhong

Chi-Tsai Chen

Wenhsien Kuo

Sheng Chi Lin

Chiu-Wang Lien

Cheng Han Lu

A circuit is disclosed. The circuit includes a first pump circuit configured to receive a first reference voltage and provide an output voltage at a first level based on the first reference voltage. The circuit includes a second pump circuit configured to receive a second reference voltage and provide the output voltage at a second level based on the second reference voltage. The first reference voltage is lower than the second reference voltage, and the first level is lower than the second level.

Voltage provision circuits and methods for operating the same

In some aspects of the present disclosure, an adder tree circuit is disclosed. In some aspects, the adder tree circuit includes a plurality of full adders (FAs) including: a first subgroup of FAs, wherein each FA of the first subgroup includes a first number of transistors; and a second subgroup of FAs, wherein each FA of the second subgroup includes a second number of transistors, the first number being greater than the second number; wherein each FA of the first subgroup receives a first input from a first one of the second subgroup of FAs and a second input from a second one of the second subgroup of FAs, and each FA provides a first output to a third one of the second subgroup of FAs and a second output to a fourth one of the second subgroup of FAs.

Low power adder tree structure

A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

MRAM reference current

An in-memory computing device includes in some examples a two-dimensional array of memory cells arranged in rows and columns, each memory cell made of a nine-transistor current-based SRAM. Each memory cell includes a six-transistor SRAM cell and a current source coupled by a switching transistor, which is controlled by input signals on an input line, to an output line associates with the column of memory cells the memory cell is in. The current source includes a switching transistor controlled by the state of the six-transistor SRAM cell, and a current regulating transistor adapted to generate a current at a level determined by a control signal applied at the gate. The control signal can be set such that the total current in each output line is increased by a factor of 2 in each successive column of the memory cells.

SRAM-based cell for in-memory computing and hybrid computations/storage memory architecture

A method for performing an in-memory computation includes: storing data in memory cells of a memory array, the data including weights for computation; determining whether an update command to change at least one of the weights is received; in response to receiving the update command, performing a write operation on the memory array to update the at least one weight; and disabling the write operation on the memory array until receiving a next update command to change the at least one weight.

Computing device, memory controller, and method for performing an in-memory computation

A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

Memory sense amplifier trimming

A memory cell includes a memory circuit and a multiplier circuit. The multiplier circuit includes an output node configured to output the output signal, a first transistor and an initialization circuit. The first transistor is coupled to the output node and the memory circuit, and is configured to receive at least the second signal. The initialization circuit is coupled to the first transistor by the output node, and is configured to initialize the multiplier circuit in response to at least a third signal or a fourth signal. The memory circuit is configured to store a first value of a first signal of a first storage node. The multiplier circuit is coupled to the memory circuit. The multiplier circuit is configured to generate an output signal in response to the first signal and a second signal. The output signal corresponds to a product of the first signal and the second signal.

Memory cell and method of operating the same

Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.

Computing-in-memory architecture

A memory device includes a plurality of magnetoresistive random-access memory (MRAM) cells including a first one-time programmable (OTP) MRAM cell. A first OTP select transistor is connected to the first OTP MRAM cell. The first OTP select transistor configured to selectively apply a breakdown current to the first OTP MRAM cell to write the first OTP MRAM cell to a breakdown state.

One time programmable (OTP) magnetoresistive random-access memory (MRAM)

A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.

Duo-level word line driver

A memory circuit includes a selection circuit, a column of memory cells, and an adder tree. The selection circuit is configured to receive input data elements, each input data element including a number of bits equal to H, and output a selected set of kth bits of the H bits of the input data elements. Each memory cell of the column of memory cells includes a first storage unit configured to store a first weight data element and a first multiplier configured to generate a first product data element based on the first weight data element and a first kth bit of the selected set of kth bits. The adder tree is configured to generate a summation data element based on each of the first product data elements.

In-memory computation circuit and method

A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.

Low-dropout voltage regulator circuit

A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.

Sense amplifier

A compute-in-memory (CIM) device has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.

Compute in memory

A memory device including a static random-access memory that includes two cross-coupled inverters and an access transistor having a gate connected to a word line. The memory device further includes one or more logic gates electrically coupled to the static random-access memory, and a non-volatile memory electrically coupled to the static random-access memory and configured to store data and be read using the static random-access memory, wherein the non-volatile memory is connected on one side to the access transistor and on another side to the two cross-coupled inverters.

Non-volatile memory based compute-in-memory cell

Growing community of inventors

Hsinchu, Taiwan

Chia-Fu Lee