Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-En Huang

Meng-Han Lin

Yi-Ching Liu

Peng-Chun Liou

Zhiqiang Wu

Chung-Wei Wu

Ya-Yun Cheng

A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a transistor coupled to a first capacitor and a second capacitor in series, respectively. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells, and wherein the logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first capacitor or second capacitor.

Back-end-of-line compatible physically unclonable function memory device and system

A semiconductor device comprising a source, and a drain spaced apart from the source in a first direction. A channel layer is disposed radially outwards of at least one radially outer surface of the source and the drain in a second direction perpendicular to the first direction, the channel layer extending in the first direction. A memory layer is disposed on a radially outer surface of the channel layer in the second direction and extending in the first direction. A contact structure is interposed between the channel layer and at least a portion of the source and/or the drain, the contact structure having a lower resistance than the channel layer.

Semiconductor memory devices and methods of manufacturing thereof

A semiconductor device, comprises a source structure comprising an active source portion, an inactive source portion spaced apart from the active source portion in a vertical direction, and a first dielectric structure interposed between the active source portion and the inactive source portion. A drain structure is spaced apart from the source structure in a first direction. A channel layer is disposed on outer surfaces of the source and the drain structures. A memory layer is disposed on an outer surface of the channel layer so as to wrap around the channel layer. At least one gate layer is in electrical communication with the active source portion.

Semiconductor devices having a dielectric embedded in source and/or drain

A memory device includes a first memory cell. The first memory cell includes: a first conductor structure extending along a lateral direction; a first memory film comprising a first portion wrapping around a first portion of the first conductor structure; and a first semiconductor film wrapping around the first portion of the first memory film. A second conductor structure extends along a vertical direction and is coupled to a first end portion of the first semiconductor film along the lateral direction. A third conductor structure extends along the vertical direction and is coupled to a second end portion of the first semiconductor film along the lateral direction.

Semiconductor memory devices with wrapped word lines

A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures have respective different thicknesses in accordance with the varying width of the first and second conductive structures.

A semiconductor device includes a first conductor structure extending along a lateral direction. The semiconductor device includes a first memory film that extends along a vertical direction and is in contact with the first conductor structure. The semiconductor device includes a first semiconductor film that extends along the vertical direction and is in contact with the first memory film. Ends of the first semiconductor film align with ends of the first memory film, respectively. The semiconductor device includes a second conductor structure extending along the vertical direction. The semiconductor device includes a third conductor structure extending along the vertical direction. The semiconductor device includes a fourth conductor structure extending along the vertical direction. The second and fourth conductor structures are coupled to the ends of the first semiconductor film, and the third conductor structure is coupled to a portion of the first semiconductor film between its ends.

Three-dimensional memory devices and methods of manufacturing thereof

Memory devices and a method of fabricating memory devices are disclosed. In one aspect, the method includes forming a plurality of first transistors in a first area and a plurality of second transistors in a second area and forming a stack over the second area. The method includes forming a memory array portion and an interface portion through the stack. The memory array portion includes memory strings and the interface portion includes first conductive structures extending along a lateral direction. The method further includes simultaneously forming second conductive structures in the first area and forming third conductive structures in the second area. The second conductive structures each vertically extend to electrically couple to at least one of the first transistors, and the third conductive structures each vertically extend through one of the memory strings to electrically couple to at least one of the second transistors.

A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.

A semiconductor die comprises: a device portion comprising an array of semiconductor devices extending in a first direction; and at least one interface portion located adjacent to an axial end of the device portion in the first direction. The at least one interface portion has a staircase profile in a vertical direction. The interface portion comprises: a stack comprising a plurality of gate layers and a plurality of insulating layers alternatively stacked on top of one another, and memory layers interposed between each of the plurality of gate layers and the plurality of insulating layers.

Semiconductor memory devices with arrays of vias and methods of manufacturing thereof

A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structuring extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The semiconductor device further comprises a first semiconductor channel extending along the vertical direction. The first semiconductor channel is disposed between the plurality of third conductive structures and the first conductive structure and between the plurality of third conductive structures and the second conductive structure. The first and second conductive structures each have a varying width along the lateral direction, and the first semiconductor channel has a doping concentration varying along the vertical direction.

Growing community of inventors

Xinfeng, Taiwan

Chia-En Huang