Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Der Chang

Yi-Jing Lee

Guan-Jie Shen

Chih-Hsiung Lin

Guo-Chiang Chi

Chih-Hung Lu

Chih-Lin Wang

Chien-Chih Lin

Wei-Chin Chen

Chao-Shuo Chen

Pin-Cheng Hsu

Ming-Chang Lee

Yi-Tung Yen

Chung-Tsun Sun

Sherry Li

Mei-Yun Wang

Fu-Kai Yang

Chien-Chih Chou

Chien-Hung Yeh

Wen-Jia Hsieh

Yi-Chun Lo

Hung-Chang Hsu

Long-Jie Hong

Tai-Yuan Wang

Yu-Ching Chang

Jung-Ting Chen

Chia-Ping Lo

Tien-Chun Wang

Chih Hsiung Lin

Chi-Hung Liao

Sheng-Liang Pan

Chun-Chieh Huang

Min-Hsiung Chiang

Fan-Yi Hsu

Shu-Wei Chung

Yi-Jing Li

Chien-Chen Liu

Chung-Wei Hung

Chen-Heng Li

Chih-Wei Kao

Hsiao-Hui Yu

Hao-Wen Hsu

Hao Wen Hsu

Dean-E Lin

A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.

Isolation structures for semiconductor devices

The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.

Ultra-thin fin structure and method of fabricating the same

The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a buffer layer between the channel layer and the substrate. The method can further include forming a recess structure in the channel layer. The recess structure can include a bottom surface over the buffer layer. The method can further include forming a first epitaxial layer over the bottom surface of the recess structure. The first epitaxial layer can include a first atomic concentration of germanium. The method can further include forming a second epitaxial layer over the first epitaxial layer. The second epitaxial layer can include a second atomic concentration of germanium greater than the first atomic concentration of germanium.

Source/drain structure for semiconductor device

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, an insulating stack formed over the substrate, a vertical structure formed through the insulating stack, a source/drain region formed over the vertical structure, and an isolation structure formed adjacent to the source/drain region and protruding the insulating stack. The source/drain region can include a first side surface and a second side surface. A lateral separation between the first side surface and the vertical structure can be greater than an other lateral separation between the second side surface and the vertical structure.

Method for forming a source/drain of a semiconductor device having an insulating stack in a recess structure

A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.

Gate feature in FinFET device

A method for forming a semiconductor device structure includes providing a substrate and forming a gate electrode on the substrate. A first contact structure is formed in and on the gate electrode. The first contact structure comprises a first portion and a second portion. The first portion is formed in the gate electrode, and the second portion is formed on the first portion.

Semiconductor device with an interconnect structure and method for forming the same

A semiconductor device includes a first fin field effect transistor (FinFET) device, the first FinFET device including a plurality of fins formed in a substrate, an epitaxial layer of semiconductor material formed on the fins forming non-planar source/drain regions, and a first gate structure traversing across the plurality of fins. The semiconductor device includes a second FinFET device, the second FinFET device including a substantially planar fin formed in the substrate, an epitaxial layer of the semiconductor material formed on the substantially planar fin and forming substantially planar source/drain regions, and a second gate structure traversing across the substantially planar fin.

Hybrid FinFET structure

A semiconductor device includes a fin structure, disposed on a substrate, that horizontally extends along a direction; and a gate feature comprising a gate dielectric layer and at least a first metal gate layer overlaying the gate dielectric layer, wherein the gate dielectric layer and the first metal gate layer traverse the fin structure to overlay a central portion of the fin structure and further extend along the direction to overlay at least a side portion of the fin structure that is located outside a vertical projection of a sidewall of the gate feature.

Gate feature in finFET device

Growing community of inventors

Hsinchu, Taiwan

Chia-Der Chang