United Microelectronics Corp.

Chia-Chun Sun

Yun-San Huang

Yu-Tse Kuo

Meng-Ping Chuang

Chien-Li Kuo

Chun-Liang Hou

Chuan-Hsien Fu

A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.

Layout configuration for memory cell array

An inverter structure is disclosed. The inverter structure includes an NMOS transistor and a PMOS transistor. Preferably, the NMOS transistor includes an n-type gate electrode and an n-type source/drain region, and the PMOS transistor includes a p-type gate electrode and a p-type source/drain region. Specifically, the n-type gate electrode and the p-type gate electrode are physically separated and electrically connected by a conductive contact.

Inverter structure and method for fabricating the same

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Taipei, Taiwan

Chia-Chun Sun