Via Technologies, Inc.

Chia-Chun Lien

Wallace Huang

Chih-Wei Hu

Yu-Tin Hsu

Chun-Cheng Wu

The invention provides a memory card detection circuit of a computer. The memory card detection circuit comprises a plurality of query pins through which a memory card is coupled to the computer and a plurality of latch circuits respectively coupled to each of the query pins. The latch circuits generates query signals indicating whether ground bounce occurs in the voltage of the query pins due to a voltage difference between two ends of the query pins shortly after the memory card is coupled to the computer through the query pins. The query signals identify the type of the memory card without waiting until ground bounce is resolved.

Memory card detection circuit and method thereof

An apparatus and method for reducing LDRQ input pin count of a low pin count (LPC) host are provided. The LPC host is series of connecting with a plurality of peripheral devices, the peripheral device having a LDRQ control device within. The LDRQ control device comprises a LDRQ to DRQ decoder, a DRQ arbiter, and a DRQ to LDRQ encoder. In the LDRQ control device, a LDRQ signal is decoded into a DRQ signal via the LDRQ to DRQ decoder and then the DRQ signal is priority arbitrated via the DRQ arbiter. Next, the arbitrated DRQ signal is transferred into a LDRQ signal via DRQ to LDRQ encoder. Following, the LDRQ signal is outputted into the next stage peripheral device or to output into a LDRQ input pin of the LPC host, so as the LPC host only need one LDRQ input pin for purposing to effectively reduce the LDRQ input pin count and lower the manufacturing cost of the LPC host.

Apparatus and method for reducing LDRQ input pin count of a low pin count host using serially coupled peripheral devices

A chipset with LPC interface and data accessing time adapting function is proposed. The chipset comprises an LPC slave controller connected to an LPC master controller in a main controller, a LPC/ISA bridge connected to the LPC slave controller and convert a data in LPC specification to a data in ISA specification, a plurality of ISA logic control units connected to the LPC/ISA bridge and controlling corresponding ISA devices, and a data accessing time adjuster connected to the LPC/ISA bridge and adjusting the time of accessing operation for an ISA or LPC device.

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Taipei, Taiwan

Chia-Chun Lien