Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Nanjing Company, Limited

Unique Materials Co., Ltd.

Chia-Chun Liao

Min-Shueh Yuan

Chao Chieh Li

Robert Bogdan Staszewski

Shih-Hsun Chang

Shu-Hui Wang

Chao-Chieh Li

Shun-Jang Liao

Chun-Sheng Liang

Yi-Jen Chen

Chih-Hsien Chang

Yu-Tso Lin

Kuang-Hsin Chen

Tsung-Yu Chiang

Wei-Shuo Ho

Chih-hsien Chang

Huan-Wei Tseng

Chun-Wei Chou

Chia-Yi Tsai

Meng-Hsuan Wu

Wen-Yuan Tsai

Tsung-Hsien Tsai

Shih-Yao Lin

Jen-Hsiang Lu

Hsueh-Jen Chang

Yen-Feng Su

Qiuyuan Wu

Li-Sheng Kao

Shuang Dai

Yu-Jui Tseng

Ting-Yu Huang

Fa Zhou

JinXin Liu

Chieh-Fu Chu

Dei-Pei Liu

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.

Circuit, chip and semiconductor device

An electronic circuit and a method for operating the electronic circuit are provided. The electronic circuit includes a digital filter and a jitter optimization device. The digital filter is configured to receive a first signal and generate a second signal by filtering the first signal. The jitter optimization device is configured to receive the second signal and generate a first parameter and a second parameter according to the second signal. The jitter optimization device is configured to provide a first feature and a second feature associated with the second signal, and the first parameter and the second parameter are generated in response to the first feature or the second feature.

Electronic circuit and method for operating the same

An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.

Methods and apparatus of charge-sharing locking with digital controlled oscillators

A method includes identifying a cell in the layout diagram as a violated cell that fails to pass one or more design rules related to IR drops, and classifying a root cause of the violated cell with a root cause class. The method also includes determining a searching area for searching safe region candidates, and finding a selected cell for moving based upon the root cause class of the root cause. The method further includes finding a safe region in the searching area for moving the selected cell, and moving the selected cell to the safe region if the safe region is found within the searching area.

Method of reducing design rule violations due to IR drops

A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

Semiconductor device and a method for fabricating the same

An electronic circuit and a method of error correction are provided. The electronic circuit includes a time-to-digital converter (TDC) and an error cancelation circuit. The TDC is configured to generate a first signal. The error cancelation circuit is configured to evaluate a majority of bit values of at least a portion of the first signal to generate a second signal. The number of transitions within the second signal is less than the number of transitions within the first signal.

Electronic circuit and method of error correction

Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO Kis a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.

Compensation technique for the nonlinear behavior of digitally-controlled oscillator (DCO) gain

A method of designing an integrated circuit (IC) device includes identifying, with a processor, a pin failing a test to determine an antenna effect, identifying, with the processor, a net corresponding to the identified pin failing the test to determine the antenna effect, and creating, with the processor, an engineering change order (ECO) script based on the identified net to insert a diode to address the antenna effect.

Integrated circuit device design method and system

Quantum dot is a semiconductor nanomaterial. The quantum dot includes a core constituted of InP, a first shell constituted of ZnSe, a second shell constituted of ZnS, and a gradient alloy intermediate layer. The core is wrapped by the first shell. The first shell is wrapped by the second shell, and the first and second shells have different materials. The gradient alloy intermediate layer is between the core and the first shell. The gradient layer includes an alloy constituted of In, P, Zn and Se. A content of the In and P gradually decreases from the core to the first shell. A content of the Zn and Se gradually increases from the core to the first shell. A particle size of the quantum dot is greater than or equal to 11 nm. The quantum dot is capable of emitting light upon excitation with a photoluminescence quantum yield equal to or more than 50%.

Semiconductor nanomaterial with high stability

A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.

Semiconductor device and manufacturing method thereof

A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.

Frequency generator and associated method

Growing community of inventors

Taipei, Taiwan

Chia-Chun Liao