Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Chu Liu

Kuei-Shun Chen

Kuei Shun Chen

Hua-Tai Lin

Chiang Mu-Chi

Chao-Cheng Chen

Chi-Kang Chang

Chung-Ming Wang

Yu Lun Liu

Yu-Lun Liu

Shiao-Chian Yeh

Ya Hui Chang

Mu-Chi Chiang

Meng-Wei Chen

Wen-Yun Wang

Ying-Hao Su

Yi-Shien Mor

Cheng-Cheng Kuo

Chih-Yang Yeh

Yu-Chung Su

Tzu-Chun Lo

Ching-Che Tsai

Jeng-Shiun Ho

Tzung-Hua Lin

Chi-Wen Hsieh

Min-Hung Cheng

Hong-Jang Wu

Hsiao-Wei Su

Han-Hsun Chang

Chie-Chieh Lin

Yi-Ko Chen

Ru-Gun Liu

Chin-Hsiang Lin

Ryan Chia-Jen Chen

Tsai-Sheng Gau

Huan-Just Lin

Wen-Chun Huang

Min-Chang Liang

Tsong-Hua Ou

Hui-Chi Huang

Hua Feng Chen

Yao-Ching Ku

Ying-Chou Cheng

Te-Chih Huang

Yu-Po Tang

Vencent Chang

Hsiao-Tzu Lu

Norman Chen

Ming-Jhih Kuo

Boren Luo

Wen-Hao Liu

Kuo-Chang Kau

Ya-Hui Chang

Bi-Fen Wu

Yuan-Yen Lo

Shang-Wern Chang

Chih-Hsiung Peng

Sheng-Yu Chang

Minchang Liang

Shu-Chen Lu

Yao-Kwang Wu

Meng Wei Chen

A method for forming a semiconductor structure includes forming a pattern having first and second line features extending in a first direction on a substrate. After depositing a photoresist layer on the substrate to cover the pattern, the photoresist layer is patterned to form a cut pattern including first and second cut features exposing portions of the respective first and second line features. In a top view, at least one of the first and second cut features is asymmetrically arranged with respect to a central axis of a corresponding first or second line feature. At least one angled ion implantation is performed to enlarge the first and second cut features in at least one direction perpendicular to the first direction. The portions of the first and second line features exposed by the respective first and second cut features are then removed.

Feature patterning using pitch relaxation and directional end-pushing with ion bombardment

A patterning process is performed on a semiconductor wafer coated with a bottom layer, a middle layer and a photoresist layer having a starting thickness. The patterning process includes: performing an exposure step including exposing the semiconductor wafer using a mask that includes a feature which produces an intermediate light exposure in a target area followed by processing that creates openings in the photoresist layer in accordance with the mask and thins the photoresist in the target area due to the intermediate light exposure in the target area leaving thinned photoresist in the target area; performing middle layer etching to form openings in the middle layer aligned with the openings in the photoresist layer, wherein the middle layer etching does not remove the middle layer in the target area due to protection provided by the thinned photoresist; and performing trim etching to trim the middle layer in the target area.

Dual critical dimension patterning

A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

Method for manufacturing semiconductor device and system for performing the same

The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.

Method of fabricating field effect transistor having non-orthogonal gate electrode

A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.

Dummy gate structure and methods thereof

Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.

Method and structure for gap filling improvement

The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.

A method for forming a pattern on a substrate is described. The method includes providing a substrate, forming a photosensitive layer over the substrate, exposing the photosensitive layer to a first exposure energy through a first mask, exposing the photosensitive layer to a second exposure energy through a second mask, baking the photosensitive layer, and developing the exposed photosensitive layer. The photosensitive layer includes a polymer that turns soluble to a developer solution, at least one photo-acid generator (PAG), and at least one photo-base generator (PBG). A portion of the layer exposed to the second exposure energy overlaps with a portion exposed to the first exposure energy.

Methods for small trench patterning using chemical amplified photoresist compositions

A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.

Method for removing semiconductor fins using alternating masks

A method includes processing a first silicon wafer using a first focus condition, the first silicon wafer comprising: a first test pattern and a second test pattern, the first test pattern and the second test pattern being different. The method further includes determining a first critical dimension for the first test pattern, determining a second critical dimension for the second test pattern, determining a delta focus value based on the first critical dimension and the second critical dimension, and processing a second silicon wafer with a second focus condition, the second focus condition based on the delta focus value.

Inline focus monitoring

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Shin-Chu, Taiwan

Chia-Chu Liu