Vanguard International Semiconductor Corporation

Chia-Ching Tung

Yeh-Sen Lin

Hung-Yi Luo

Huey-Chi Chu

Cheng-Lung Lu

A method for forming a capacitor on a substrate is disclosed herein. The method according to the present invention can increase the capacitance of a capacitor in one interface-etching process, the method mention above includes the following step. The first step is to form a storage node in a dielectric layer on the substrate, wherein the bottom of a cubic portion of the storage node faces the substrate is buried in the dielectric layer, and the storage node is coupled to the substrate. Next, interface-etching the dielectric layer to expose the surface including the bottom of the cubic portion of the storage node. In etching the dielectric layer made of BPSG, the buffer oxide etching (B.O.E) is utilized. Then an insulating layer is formed on the exposed surface including the bottom of the cubic portion of the storage node. Finally, a conductive layer is formed on the insulating layer. The storage node, the insulating layer, and the conductive layer constitute the capacitor.

Method for fabricating a capacitor

The present invention discloses a method for eliminating leakage current in a semiconductor device by preventing silicon loss in a first area of a substrate during fabricating the semiconductor device. The method according to the preferred embodiment of the present invention includes the following steps. Firstly, form a first gate structure on a second area of the substrate, and form a first structure together with a second structure on the first area of the substrate. Then form a dielectric layer on the topography of the wafer. Next, etch a thickness of the dielectric layer until about 200-1000 angstroms in thickness of the dielectric layer is remained. Subsequently, form a photoresist pattern on the first area of the substrate, and etch the exposed second portion of the dielectric layer to form spacers of the first gate structure. The spacers and the gate structure constitute a gate electrode of a first transistor. Next, form a source region and a drain region in the substrate, wherein the gate electrode, the source region, and the drain region constitute a first transistor, then remove the photoresist pattern. Finally, form a second transistor, a capacitor, and a control line in the first area of the substrate, wherein the first structure and the second structure is formed on the first area of the substrate.

Method for preventing silicon substrate loss in fabricating semiconductor device

A method for avoiding micro-loading effect during etching is disclosed. The method comprises the steps of: providing a semiconductor substrate with a layer to be patterned and etched formed thereover; forming a masking layer over the layer to be patterned; defining a row pattern in the masking layer, the row pattern comprising a plurality of rectangles and a plurality of connecting bars, each of the connecting bars connecting two of the rectangles; and removing a portion of the layer to be patterned, to form a patterned layer with a recessed channel, by using the masking layer as a mask with the row pattern.

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Kaohsiung, Taiwan

Chia-Ching Tung