United Microelectronics Corp.

Academia Sinica

Chia-Ching Lin

En-Chiuan Liou

Tang-Chun Weng

Yen-Pu Chen

Ssu-I Fu

Shih-Hung Tsai

Chih-Wei Yang

Chia-Lin Lu

Rai-Min Huang

Chien-Hao Chen

Jim-Min Fang

Chih-Cheng Chen

Chun-Chi Yu

Chia-Hung Wang

Sho-Shen Lee

Yun-Lian Lin

Chia-Hsun Tseng

Kuei-Chun Hung

Yijuang Chern

Yi-Jing Wang

Hsiao-Lin Hsu

Chun-Jung Lin

Cheng-Hao Yang

Wei-Nan Chen

Wei-Jhe Tzai

A method for monitoring fin removal includes providing a substrate having a first region with first fins extending along a first direction and a second region with second fins extending along a second direction, wherein the first direction is perpendicular to the second direction; forming a material layer on the substrate to cover the first fins and the second fins; identically patterning the first fins and the second fins using a first pattern and a second pattern respectively for simultaneously removing parts of the first and second fins, thereby forming first fin features in the first region and second fin features in the second region, wherein the first pattern has a first dimension along the second direction, the second pattern has a second dimension along the second direction, and the second dimension is equal to the first dimension; and monitoring the first fin features using the second fin features.

Method for monitoring fin removal

Methods for treating pain such as fibromyalgia, comprising administering to a subject in need thereof an effective amount of an adenosine analog, wherein the adenosine analog may be a compound of Formula (I): 

Methods and compositions for treating pain

A semiconductor structure includes a semiconductor substrate with a first region and a second region defined thereon. The first region is disposed adjoining the second region in a first direction. The semiconductor substrate includes fin structures, first recessed fins, and a bump. The fin structures are disposed in the first region. Each fin structure is elongated in the first direction. The first recessed fins are disposed in the second region. Each first recessed fin is elongated in the first direction. A topmost surface of each first recessed fin is lower than a topmost surface of each fin structure. The bump is disposed in the second region and disposed between two adjacent recessed fins in the first direction. A topmost surface of the bump is higher than the topmost surface of each first recessed fin and lower than the topmost surface of each fin structure.

Semiconductor structure

A method of fabricating a semiconductor structure is provided and includes the following steps. A semiconductor substrate including fin structures is provided. Each fin structure is partly located in a first region and partly located in a second region adjoining the first region. A fin remove process is performed for removing the fin structures in the second region. A fin cut process with a fin cut mask is performed for cutting a part of the fin structures in the first region. The fin cut mask includes cut patterns and a compensation pattern. The cut patterns are located corresponding to a part of the fin structures in the first region. The compensation pattern is located corresponding to the second region of the semiconductor substrate. A fin bump is formed in the second region and corresponding to the compensation pattern after the fin cut process and the fin remove process.

Method of fabricating semiconductor structure

The present invention provides a semiconductor structure, including a substrate, a shallow trench isolation (STI) disposed in the substrate, a plurality of first fin structures disposed in the substrate, where each first fin structure and the substrate have same material, and a plurality of second fin structures disposed in the STI, where each second fin structure and the STI have same material.

Semiconductor structure and manufacturing method thereof

An overlay operation method and an overlay control method are disclosed. A first mark and a second mark are identified on a substrate, wherein the first mark and the second mark are formed by a process in combination with using a photomask. Next, a first measurement is performed to obtain an offset between the first mark and the second mark in a direction. Then, an operation is performed to judge whether the offset is in a range from a pre-determined offset minus a deviation to the pre-determined offset plus the deviation, wherein the pre-determined offset is determined by the photomask.

Overlay operation method and overlay control method

An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.

Overlay marks and semiconductor process using the overlay marks

A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.

Measurement method of overlay mark

Growing community of inventors

Kaohsiung, Taiwan

Chia-Ching Lin