Taiwan Semiconductor Manufacturing Comp. Ltd.

Wistron Corporation

Mediatek Incorporation

Chia-Ching Lee

Chung-Chiang Wu

Da-Yuan Lee

Ching-Hwanq Su

Hsueh Wen Tsau

Hung-Chin Chung

Chien-Hao Chen

Chi-Cheng Hung

Yu-Sheng Wang

Shih-Hang Chiu

Cheng-Lung Hung

Hsien-Ming Lee

Mrunal Abhijith Khaderbad

Hsuan-Yu Tung

Cheng-Yen Tsai

Wei-Chin Lee

Hsin-Han Tsai

Hsueh-Wen Tsau

Chi On Chui

Jhih-Ming Chen

Kuan-Chang Chiu

Huicheng Chang

Huan-Just Lin

Kuo-Feng Yu

Weng Chang

Sheng-Liang Pan

Jian-Hao Chen

Chih-Chang Hung

Chia-Wei Chen

Hsiao-Kuan Wei

Shao-Jyun Wu

Chun-Yuan Chou

Chih-Yu Hsu

Liang Yu

Tsung-Ta Tang

Pin-Hsuan Yeh

Ta-Chun Hsiung

Hung-Chi Wu

Ming-Hsing Tsai

Cheng-Hsiang Chuang

Kuo Hui Chang

Chen Liang Chang

Wen-Yi Tsai

Xiu-Feng Cheng

Min-Hao Tang

Shou-Yi Cheng

Wen-Jui Lin

Xing Liu

Wei-Chou Hung

Kou-Chih Peng

Chi-Chun Peng

Young-Wei Lin

Yu Liang Huang

Po-Yu Su

At least one embodiment, a vacuum chuck includes a moisture gate structure that allows for moisture to escape to reduce an amount of warpage in a workpiece when present on the vacuum chuck. The moisture gate structure includes a base portion that extends laterally outward from a central vacuum portion of the vacuum chuck, and a plurality of protrusions are spaced apart from the central vacuum portion and extend outward from the base portion. End surfaces of the plurality of protrusions contact a backside surface of the workpiece (e.g., a wafer on a carrier) when the workpiece is present on the vacuum chuck. The vacuum chuck may further include one or more guide portions that act as guides such that the workpiece remains properly aligned and within position when present on the vacuum chuck.

Vacuum chuck

A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

FinFET structures and methods of forming the same

A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

Semiconductor device with a work function layer having an oxygen-blocking dopant layer

A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Semiconductor device and method of manufacture

An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Semiconductor device and method

A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

Method of tuning threshold voltages of transistors

Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.

Contact plug with impurity variation

A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.

Controlling threshold voltages through blocking layers

Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.

Geometry for threshold voltage tuning on semiconductor device

A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.

Semiconductor device and methods of manufacture

Growing community of inventors

Taipei, Taiwan

Chia-Ching Lee