Vanguard International Semiconductor Corporation

Chia-Ching Huang

Shin-Cheng Lin

Chih-Yen Chen

Hsin-Chih Lin

Yung-Hao Lin

Chun-Yi Wu

Chang-Xiang Hung

Chia-Hao Lee

Chih-Jen Hsiao

Fu-Hsin Chen

Wei-Chan Chang

Franky Juanda Lumbantoruan

Francois Hebert

Shin-Chen Lin

Yang Du

Walter Wohlmuth

Hsin-Chang Tsai

A semiconductor device includes a substrate having an active element region and a passive element region. A compound semiconductor channel layer, a compound semiconductor barrier layer and a first compound semiconductor cap layer are disposed in sequence on the substrate and located in the active element region. A gate electrode is disposed on the first compound semiconductor cap layer. A source electrode and a drain electrode are disposed on the compound semiconductor barrier layer and located on two opposite sides of the gate electrode, respectively, to construct a high electron mobility transistor. A second compound semiconductor cap layer is disposed on the substrate and located in the passive element region to construct a resistor.

Semiconductor device and fabrication method thereof

A semiconductor device includes an insulating layer, a semiconductor layer, and a compound semiconductor stacked layer disposed on a substrate in sequence, a first transistor, a second transistor, an isolation structure, and a conductive structure. The first transistor is disposed in a first device region and on the compound semiconductor stacked layer. The second transistor is disposed in a second device region and on the compound semiconductor stacked layer. The isolation structure is disposed between the first and second transistors. The conductive structure is disposed in the second device region, passes through the compound semiconductor stacked layer, and electrically connects the semiconductor layer to a second source of the second transistor. There is no electrical connection between the semiconductor layer in the first device region and a first source of the first transistor.

Semiconductor device including high electron mobility transistors with an improved backside electrode being applied in a half-bridge circuit

A high electron mobility transistor includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate field plate, a source electrode, at least one first field plate, and a second field plate. The gate field plate is disposed on the semiconductor barrier layer. The source electrode is disposed on one side of the gate field plate, and the first field plate is disposed on the other side of the gate field plate and laterally spaced apart from the gate field plate. The second field plate covers the gate field plate and the first field plate and is electrically connected to the source electrode, where the area of the second field plate is larger than the sum of the area of the gate field plate and the area of the first field plate when perceived from a top-down perspective.

High electron mobility transistor

A high electron mobility transistor includes a substrate, a compound semiconductor stacked layer, a cap layer, a gate electrode, a source electrode, a drain electrode, and a buried electrode and/or a conductive structure. The substrate has an active area. The cap layer is disposed on the compound semiconductor stacked layer. The gate electrode is disposed on the cap layer and extends along a first direction. The source electrode and the drain electrode are disposed on the compound semiconductor stacked layer, respectively on two sides of the gate electrode, and arranged along a second direction, where the first direction is perpendicular to the second direction. The conductive structure and/or the buried electrode passes through the compound semiconductor stacked layer and surrounds or lies in the active area, where the conductive structure and/or the buried electrode has a constant electric potential or is grounded.

A semiconductor device is provided, including a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, an electrode structure on the epitaxial layer and an electric field modulation structure. The electrode structure includes a gate structure, a source structure and a drain structure, wherein the source structure and the drain structure are positioned on opposite sides of the gate structure. The electric field modulation structure includes an electric connection structure and a conductive layer electrically connected to the electric connection structure. The conductive layer is positioned between the gate structure and the drain structure. The electric connection structure is electrically connected to the source structure and the drain structure.

Semiconductor device

A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other.

A semiconductor device is provided. The semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a compound semiconductor layer disposed over the barrier layer, a gate electrode disposed over the compound semiconductor layer, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. The source electrode and the drain electrode penetrate through at least a portion of the barrier layer. The semiconductor device also includes a source field plate connected to the source electrode through a source contact. The semiconductor device further includes a first electric field redistribution pattern disposed on the barrier layer and directly under the edge of the source field plate.

Semiconductor devices and methods for fabricating the same

A high electron mobility transistor includes a channel layer, a barrier layer, a first compound semiconductor layer, and a second compound semiconductor layer. The channel layer is disposed on the substrate, and the barrier layer is disposed on the channel layer. The first compound semiconductor layer is disposed on the barrier layer. The second compound semiconductor layer is disposed between the barrier layer and the first compound semiconductor layer, where the first compound semiconductor layer and the second compound semiconductor layer include a concentration distribution of metal dopant, and the concentration distribution of metal dopant includes a first peak in the first compound semiconductor layer and a second peak in the second compound semiconductor layer.

A high-electron mobility transistor (HEMT) includes a substrate, a group III-V channel layer, a group III-V barrier layer, a group III-V cap layer, a source electrode, a first drain electrode, a second drain electrode, and a connecting portion. The group III-V channel layer, the group III-V barrier layer, and the group III-V cap layer are sequentially disposed on the substrate. The source electrode is disposed at one side of the group III-V cap layer, and the first and second drain electrodes are disposed at another side of the group III-V cap layer. The bottom surface of the first drain electrode is separated from the bottom surface of the second drain electrode, and the composition of the first drain electrode is different from the composition of the second drain electrode. The connecting portion is electrically coupled to the first drain electrode and the second drain electrode.

A semiconductor structure is provided. The semiconductor structure includes a base, a seed layer, a compound semiconductor layer, a gate structure, a source structure, a drain structure, and a conductive paste. The seed layer is disposed on the base. The compound semiconductor layer is disposed on the seed layer. The gate structure is disposed on the compound semiconductor layer. The source structure and the drain structure are disposed on both sides of the gate structure. In addition, the conductive paste is disposed between the base and a lead frame, and the conductive paste extends to the side surface of the base.

Semiconductor structure employing conductive paste on lead frame

A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other. A method for fabricating the semiconductor device is also provided.

A semiconductor device includes a semiconductor layer, a gate electrode disposed on the semiconductor layer, a first dielectric layer disposed on the semiconductor layer and the gate electrode, a source field plate disposed on the semiconductor layer and the first dielectric layer, a second dielectric layer disposed on the source field plate, and a source electrode disposed on the second dielectric layer and electrically connected to the source field plate. The gate electrode has a first sidewall and a second sidewall respectively disposed on the first side and the second side. The source field plate extends from the first side to the second side. A portion of the source field plate is disposed to correspond to the second sidewall. The semiconductor device further includes a third dielectric layer disposed on the source electrode and a drain structure disposed on the second side.

Semiconductor device and operating method thereof

A semiconductor structure includes a substrate, a gate structure disposed on the substrate, a source structure and a drain structure disposed on opposite sides of the gate structure, and a first dielectric layer. The gate structure includes a gate electrode disposed on the substrate and a gate metal layer electrically connected to the gate electrode and serving as a gate field plate. The source structure includes a source electrode disposed on the substrate and a first source metal layer electrically connected to the source electrode and extending in the direction from the gate electrode to the drain structure. The first dielectric layer is disposed on the gate metal layer. The electric potential of the first source metal layer is different from that of the gate metal layer. The first source metal layer exposes at least a portion of the first dielectric layer directly above the gate metal layer.

Semiconductor structure

A high electron mobility transistor includes a buffer layer, a threshold voltage adjustment layer, a band adjustment layer, a first enhancement layer, a gate electrode, and source/drain electrodes. The threshold voltage adjustment layer is disposed on the buffer layer. A channel region is disposed in the buffer layer adjacent to an interface between the buffer layer and the threshold voltage adjustment layer. The band adjustment layer is disposed on the threshold voltage adjustment layer. The first enhancement layer is conformally covering the threshold voltage adjustment layer and the band adjustment layer. The gate electrode is disposed on the first enhancement layer. The source/drain electrodes are disposed on the buffer layer through the threshold voltage adjustment layer and the first enhancement layer on opposite sides of the gate electrode respectively. The threshold voltage adjustment layer and the first enhancement layer are III-V semiconductors.

A high hole mobility transistor includes a substrate, a back-barrier layer, a conducting layer, a doping layer, a gate electrode, source/drain electrodes, and a band adjustment layer. The back-barrier layer is disposed on the substrate. The conducting layer is disposed on the back-barrier layer. A channel region is disposed in the conducting layer and is adjacent to the interface between the conducting layer and the back-barrier layer. The doping layer is disposed on the conducting layer. The gate electrode is disposed on the doping layer. The source/drain electrodes are disposed on opposite sides of the gate electrode. The band adjustment layer is disposed on the doping layer and electrically connected to the gate electrode. The band adjustment layer is an N-type doped III-V semiconductor.

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Taoyuan, Taiwan

Chia-Ching Huang