United Microelectronics Corp.

Chia-Ching Hsu

Shen-De Wang

Wang Xiang

Ko-Chi Chen

Liang Yi

Chun-Sung Huang

Weichang Liu

Wen-Peng Hsu

Wei-Chang Liu

Guoan Du

Yung-Lin Tseng

A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming said RRAM device.

Resistive random-access memory (RRAM) device and forming method thereof

A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

Silicon-oxide-nitride-oxide-silicon (SONOS) memory cell and forming method thereof

A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.

Semiconductor device with integrated memory devices and MOS devices and process of making the same

A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.

Memory device and method for fabricating the same

A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a-like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the-like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.

Structure of semiconductor device and method for fabricating the same

A method of integrating memory and metal-oxide-semiconductor (MOS) processes is provided, including steps of forming an oxide layer and a nitride layer on a substrate, forming a field oxide in a first area by an oxidation process with the nitride layer as a mask, wherein the oxidation process simultaneously forms a top oxide layer on the nitride layer, removing the top oxide layer, the nitride layer and the oxide layer in the first area, forming a polysilicon layer on the substrate, and patterning the polysilicon layer into MOS units in the first area and memory units in a second area.

A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; forming a second gate structure on the substrate and on one side of the first gate structure; forming a third gate structure on the substrate and on another side of the first gate structure; forming source/drain regions adjacent to the second gate structure and the third gate structure; and forming contact plugs to contact the first gate structure, the second gate structure, the third gate structure, and the source/drain regions.

Semiconductor device and method for fabricating the same

A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.

Memory structure

A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (TMO) layer formed on the bottom electrode, a TMO sidewall oxides formed at sidewalls of the TMO layer, a top electrode formed on the TMO layer, and spacers formed on the bottom electrode. The upper conducting layer is formed on the top electrode and electrically connected to the top electrode.

Semiconductor device having memory cell structure and method of manufacturing the same

A method of fabricating a semiconductor device includes providing a substrate with a memory region and a logic region, forming a recess of the substrate in the memory region, forming a non-volatile gate stack in the recess, and forming a logic gate stack in the logic region after forming the non-volatile gate stack.

Semiconductor device and method of fabricating semiconductor device

A semiconductor device includes an interconnection formed above a substrate, and the interconnection comprising interconnect layers respectively buried in dielectric layers; a lower conducting layer formed above the substrate; a memory cell structure formed on the lower conducting layer and buried in one of the dielectric layers; an upper conducting layer formed on the memory cell structure. The memory cell structure includes a bottom electrode formed on and electrically connected to the lower conducting layer; a transitional metal oxide (TMO) layer formed on the bottom electrode; and a top electrode formed on the TMO layer, wherein the upper conducting layer is formed on the top electrode and electrically connected to the top electrode. Also, the lower conducting layer and the upper conducting layer are positioned in the different dielectric layers.

Semiconductor device having memory cell structure

A resistive random access memory includes a lower electrode, an upper electrode and a resistive layer between the lower electrode and the upper electrode, wherein the resistive layer includes a constant-resistance portion and a variable-resistance portion surrounding the constant-resistance portion.

Resistive random access memory and method of forming the same

The present invention provides a semiconductor device. The semiconductor device includes a contact structure disposed in a first dielectric layer, a second dielectric layer disposed on the first dielectric layer and having an opening disposed therein, a spacer disposed in the opening and partially covering the contact structure, and a resistive random-access memory (RRAM) disposed on the contact structure and directly contacting the spacer, wherein the RRAM includes a bottom electrode, a top electrode, and a switching resistance layer disposed between the bottom electrode and the top electrode.

Semiconductor device and method of making the same

A semiconductor device includes a substrate with a memory region and a logic region, a logic gate stack, and a non-volatile gate stack. The substrate has a recess disposed in the memory region. The logic gate stack is disposed in the logic region and has a first top surface. The non-volatile gate stack is disposed in the recess and has a second top surface. The second top surface is lower than the first top surface by a step height.

A split gate NVM device includes a semiconductor substrate, an ONO structure disposed on the semiconductor substrate, a first gate electrode disposed on the ONO structure, a second gate electrode disposed on the semiconductor substrate, adjacent to and insulated from the first gate electrode and the ONO structure, a first doping region with a first conductivity formed in the semiconductor substrate and adjacent to the ONO structure, a second doping region with the first conductivity formed in the semiconductor substrate and adjacent to the second gate electrode, and a third doping region with the first conductivity formed in the semiconductor substrate, disposed between the first doping region and the second doping region and adjacent to the ONO structure and the second gate electrode.

Growing community of inventors

Yunlin County, Taiwan

Chia-Ching Hsu