National Yang Ming Chiao Tung University

Asolid Technology Co., Ltd.

Chia-Ching Chu

Hsie-Chia Chang

Yi-Min Lin

Chi-Heng Yang

A memory controller includes a damaged-column manager, an error checking and correcting decoder (ECC decoder) and a damaged-column decision circuit. The damaged-column manager logs a damaged-column address information in the flash memory. The ECC decoder receives a read data read by the flash memory and generates an error information according to whether or not the read data has error. The damaged-column decision circuit receives the error-column address and counts the number of accumulated generated times corresponding to the error-column address. The damaged-column decision circuit updates the damaged-column address information according to an error information.

Flash memory apparatus, memory controller and method for controlling flash memory

A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture.

Growing community of inventors

Taichung, Taiwan

Chia-Ching Chu