Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Chia Kan

Po-Tao Chu

Pei-Hsuan Lee

Shen-Ping Wang

Lieh-Chuan Chen

Yuan-Yao Chang

Yu-Hsuan Huang

Tzu-Ming Huang

Wei-Jhih Wang

Chia Wei Huang

The present disclosure provides a method of analyzing a semiconductor device. The method includes providing a first transistor, a second transistor disposed adjacent to the first transistor, and a gate electrode common to the first transistor and the second transistor; connecting a power-supply voltage (V) to the gate electrode to turn on the first transistor, determining a first threshold voltage (V) based on the power-supply voltage; switching the power-supply voltage to a ground voltage (V); connecting the ground voltage to the gate electrode to turn on the second transistor; and determining a second threshold voltage based on the ground voltage.

Semiconductor device and analyzing method thereof

A method includes: coupling a first end of a first conductive trace to a free electron source; scanning exposed surfaces of the first and a second conductive traces with an electron beam, the first conductive trace and a second conductive trace being alternately arranged and spaced apart; obtaining an image of the first conductive trace and the second conductive trace while performing the scanning; and determining a routing characteristic of the first conductive trace and the second conductive trace based on the image.

Wafer-level testing method and test structure thereof

Embodiments for the present disclosure include a semiconductor device, an ultra-high voltage (UHV) laterally-diffused metal-oxide-semiconductor (LDMOS) transistor, and methods of forming the same. An embodiment includes a first well region of a first conductivity type in a top surface of a substrate, and a second well region of a second conductivity type in the top surface of the substrate. The second well region laterally separated from the first well region by a portion of the substrate. The embodiment further includes a third region of the second conductivity type in the first well region, and a first field oxide region in the first well region, a second field oxide region in the second well region, the second field oxide region having a second bottom surface, and the first field oxide region having a first bottom surface lower than the second bottom surface and on and directly contacting the third region.

Ultra-high voltage laterally-diffused MOS devices and methods of forming the same

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Taipei, Taiwan

Chia-Chia Kan