Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Semiconductor Manf. Intl. (shanghai) Corporation

Semiconductor Manf. Intl. (beijing) Corporation

Semiconductor Manufacturing International Corp.

Chia Chi Yang

Zhi Bing Deng

Cheng-Tai Huang

Chen-Yi Huang

Wen Jun Weng

Chen Yi Huang

Teng Ye Wang

Cheng Yi Huang

Xian Zhang

Fei Liu

Hua Tang

Dong Luo

Haifeng Yang

Jun Tao Guo

Benpeng Xun

Circuits and methods for measuring a working current of a circuit module. An exemplary circuit for measuring a working current of a circuit module includes a capacitor. The capacitor supplies a voltage to the circuit module using a voltage on the two terminals of the capacitor. The circuit also includes a voltage measuring module. The voltage measuring module measures a voltage change amount on the two terminals of the capacitor in an unit time. The working current of the circuit module is determined by the circuit according to the voltage change amount on the two terminals of the capacitor in the unit time and a capacitance of the capacitor.

Circuit and method for measuring working current of circuit module

A Static Random Access Memory (SRAM) array power supply circuit is presented. The circuit comprises an SRAM test unit having a substantially same structure as a basic SRAM unit in the SRAM array; a switch device connected to a power source, the SRAM test unit, and the SRAM array; and a switch control circuit connected to the SRAM test unit and the switch device. When a test voltage in the SRAM test unit is lower than a threshold voltage, the switch device is closed so that the power source begins to charge the SRAM array and the SRAM test unit. The SRAM test unit provides an early warning for the SRAM array, allowing the latter to be charged upon fulfillment of a condition (e.g., charge is low). Compared to conventional circuits, this circuit provides an output voltage that is more stable and less susceptible to the changes in external conditions such as temperature or pressure.

Static random access memory (SRAM) array power supply circuit

Method and device for detecting the process corner of a transistor are provided. The process corner detection method includes providing a ring oscillator. The ring oscillator includes an odd number of oscillation units connected in series and an output port of one of the oscillation units serves as the output port of the ring oscillator to output an oscillation signal. Each oscillation unit is constructed based on a PMOS transistor and an NMOS transistor. The process corner detection method further includes measuring the period of the oscillation signal and the maintaining time of the oscillation signal at a high level and a low level in each cycle; and determining the process corner of the PMOS transistor and the NMOS transistor in the oscillation unit based on the period of the oscillation signal and the maintaining time of the oscillation signal at a high level and a low level in each cycle.

Detection method and detection device of process corner of mos transistor

A method operates a bandgap voltage reference circuit that includes a bias circuit for receiving a feedback signal and outputting a bias signal, an amplifier for receiving the bias signal and outputting a first reference signal as the feedback signal, an output circuit for receiving the first reference signal and outputting a second reference signal, and an output switch for outputting the second reference signal as an output signal. The method includes, after powering up the bandgap voltage reference circuit, determining whether the output signal is stable, when the output signal is stable, turning off the output switch; turning off the bias circuit; and turning off the output circuit. The sequential turning off the output switch, the output circuit, and the bias circuit puts the bandgap voltage reference circuit into a sleep mode to save power.

Bandgap with system sleep mode

Level-shifter circuits and methods of using the same are provided. A level-shifter circuit includes a latch unit and a level-shifting unit. The latch unit is configured to generate a latch signal for storing a logic state of a first digital signal in a first power supply domain. The level-shifting unit is configured to shift a voltage of the latch signal to output a second digital signal in a second power supply domain. The latch unit and the level-shifting unit are powered by a power supply voltage in the second power supply domain.

Level-shifter circuits and methods of using the same

The present disclosure relates to the field of intelligent wearable technologies, and provides a power supply circuit, a power supply circuit generation method, and a power supply circuit control method. The present disclosure provides a power supply circuit, including: a bandgap voltage reference Bandgap, a real-time detection and control module, and an alternate voltage source module, where the real-time detection and control module adjusts an output point voltage of the alternate voltage source module according to an output voltage of the Bandgap; and when the output point voltage of the alternate voltage source module reaches a target voltage, the real-time detection and control module closes the Bandgap and supplies power by using the alternate voltage source module. In such a power supply circuit, after adjustment of an output point voltage of an alternate voltage source module is completed, a Bandgap does not need to keep a power-supply state, and therefore power consumed by the Bandgap is reduced based on stable voltage supply.

Power supply circuit, power supply circuit generation method, and power supply circuit control method

A power supply circuit, its generating and control methods are presented, relating to smart wearable devices. The power supply circuit comprises a Bandgap voltage reference, a real-time detection and control circuit, and a substitute voltage source. The real-time detection and control circuit is connected to the Bandgap voltage reference and the substitute voltage source, and adjusts an output voltage of the substitute voltage source to match an output voltage of the Bandgap voltage reference. After these output voltages are equal, the output voltage of the power supply circuit is provided by the substitute voltage source, and the Bandgap voltage reference can be disconnected from the circuit. This circuit can lower the power consumption of the Bandgap voltage reference without affecting the stability of the voltage output.

Power supply circuit and a method of controlling the same

The present disclosure provides Efuse bit cells and read/write methods thereof, and Efuse arrays. An exemplary Efuse bit cell includes a data latch configured to latch data of the Efuse bit cell, having two branches with a fuse disposed in a first branch and a resistor disposed in a second branch; a selection controller configured to control connections between one terminal of the first branch and a power source and between one terminal of the second branch and the power source, another terminal of the first branch and another terminal of the second branch being connected to ground; a first diode and a second diode, one of the first diode and the second diode being configured to input a write data signal; and a pass unit configured to transmit data stored in the Efuse bit cell and output a bit line signal.

Efuse bit cell, and read/write method thereof, and efuse array

The present disclosure provides circuits and methods for generating clock-signals. An exemplary clock-signal generation circuit includes a delay buffer unit; an inverter unit coupled to the delay buffer unit; a first delay unit having a first NAND Boolean calculation sub unit, a first sub delay unit and a first level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a first delayed clock-signal; and a second delay unit having a second NAND Boolean calculation sub unit, a second sub delay unit and a second level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a second delayed clock signal.

Circuit and method for generating clock-signals

An electrical fuse (eFuse) array includes eFuse cells arranged in multiple rows and columns. Each eFuse cell has an eFuse, a first diode, and a second diode coupled to an internal node, each eFuse cell further having first, second, and third terminals coupled, respectively, to the first diode, the second diode, and the eFuse. The eFuse array further includes a shared NMOSFET for each of the multiple rows, with a drain coupled to the third terminal of each of the plurality of eFuse cells in that row and a gate coupled to a word line. Each column includes a write bit line coupled to the second terminal of each of the eFuse cells in that column, and a read bit line coupled to the first terminal of the eFuse cell.

Method and device for compact eFuse array

A array of electrically programmable fuse (eFuse) units includes at least one connecting switch connecting two adjacent eFuse units. Each eFuse unit includes an eFuse, a write switch for passing through a first portion of a write current, a read/write switch for passing through a second portion of the write current or a read current, and a common node. The eFuse, the write switch, the read/write switch, and the at least one connecting switch are connected to each other at the common node. By turning on and off the at least one connecting switch, the current is split among the eFuse units, so that the size of the write switch can be reduced, thus reducing the total area of the array.

Growing community of inventors

Shanghai, China

Chia Chi Yang