Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Chia-Chi Chung

Chih-Hsien Hsu

Ying-Hao Wang

Yu-Shine Lin

Yu-Xiang Lin

Yu-Hen Wu

Han-Chih Chung

Han Wen Hsu

Chun-Hung Lee

Neng-Kuo Chen

Jeff J Xu

Ming-Chung Liang

Hsin-Chih Chen

Henry Chung

Wen-Chih Chen

Chen-Huang Huang

Yu-Pei Chiang

Jr-Sheng Chen

Shin-Yi Tsai

Chun Yan Chen

Lin-Ching Huang

Chin-Han Meng

Chung-Hsiu Cheng

Kuo-Chin Liu

Wei-Da Chen

Chien-Hua Tseng

Wei-Yueh Tseng

Jerry Lai

Huan-Lisng Tzeng

Shiuh-Sheng Yu

Chien-Sheng Wu

Tien-Chih Huang

Shih-Hao Wu

Ya-Ping Su

Han-Wen Fung

Kuo-Yen Chang

Zhi-Sheng Xu

A method for making a semiconductor device is disclosed. A substrate comprising semiconductor device elements is provided. A top conductive pad and an anti-reflective coating are patterned over the substrate. The anti-reflective coating is disposed on the top conductive pad. At least one passivation film is formed over the substrate and the anti-reflective coating. The at least one passivation film and the anti-reflective coating are etched to form a trench therein so as to expose a portion of the top conductive pad.

Method of forming a semiconductor device comprising top conductive pads

Various embodiments of the present application are directed towards an edge-exposure tool with a light emitting diode (LED), as well as a method for edge exposure using a LED. In some embodiments, the edge-exposure tool comprises a process chamber, a workpiece table, a LED, and a controller. The workpiece table is in the process chamber and is configured to support a workpiece covered by a photosensitive layer. The LED is in the process chamber and is configured to emit radiation towards the workpiece. A controller is configured to control the LED to expose an edge portion of the photosensitive layer, but not a center portion of the photosensitive layer, to the radiation emitted by the LED. The edge portion of the photosensitive layer extends along an edge of the workpiece in a closed path to enclose the center portion of the photosensitive layer.

Edge-exposure tool with an ultraviolet (UV) light emitting diode (LED)

In some embodiments, a maintenance apparatus is provided for maintaining semiconductor processing equipment. The maintenance apparatus has an articulated member having a first member with a handle engagement portion and a second member with a first tool engagement portion. The first member is rotationally coupled to the first member about an articulation axis. A first tool member in selective engagement with the first tool engagement portion of the second member.

Multi-function multi-angle cleaning tool

A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a second substrate over a first substrate, and a cavity is formed between the first substrate and the second substrate. The method includes forming a hole through the second substrate using an etching process, and the hole is connected to the cavity. The etching process includes a plurality of etching cycles, and each of the etching cycles includes an etching step, and the etching step has a first stage and a second stage. The etching time of each of the etching steps during the second stage is gradually increased as the number of etching cycles is increased.

Method for forming micro-electro-mechanical system (MEMS) device structure

A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.

Method of forming a layer on a semiconductor substrate having a plurality of trenches

A method is disclosed for etching an integrated circuit structure within a trench. A layer to be etched is applied over the structure and within the trench. A CF-based polymer is deposited over the layer to be etched followed by deposition of a capping layer of SiOCl-based polymer. The CF-based polymer reduces the width of the trench to such an extent that little or no SiOCl-based polymer is deposited at the bottom of the trench. An Oplasma etch is performed to etch through the CF-based polymer at the bottom of the trench. The Oplasma etch has little effect on the SiOCl-based polymer, the thus the upper surfaces of the structure remain covered with polymer. Thus, these upper surfaces remain fully protected during subsequent etching of the layer to be etched.

Method for etching integrated circuit structure

Methods for making a nonvolatile memory device, such as an NROM device that has an oxide-nitride-oxide layer beneath at least one word line structure, are disclosed. The oxide-nitride-oxide layer is in the form of a plurality of oxide-nitride block structures disposed over an oxide layer, with each of the oxide-nitride block structures overlapping two adjoining bit lines. A dielectric resolution enhancement coating technique is performed to precisely control the oxide-nitride block structure dimensions.

Non-volatile memory device with enlarged trapping layer

The present invention generally relates to a dual damascene processing method using a silicon rich oxide (SRO) layer thereof and its structure. In the dual damascene process, a first dielectric layer, an etching stop layer, such as a silicon rich oxide layer, and a second dielectric layer are sequentially formed on a semiconductor substrate, which is provided with metal connections therein. Then, the present invention utilizes photolithography and etching technique to obtain a dual damascene structure profile having a trench and a via hole. The present invention uses the silicon rich oxide layer as the etching stop layer so as the present invention can achieve a better trench microloading and better bottom profile. Beside, the present invention does not increase the dielectric constant index (K) of the inter metal dielectric (IMD).

Dual damascene processing method using silicon rich oxide layer thereof and its structure

A method is disclosed for forming a semiconductor structure with conductive features having reduced dimensional spacing or pitch. First polymer layers are formed over photoresist features to facilitate patterning of both an underlying first dielectric and conductive layer into first dielectric features and conductive features. Second dielectric features are then formed in spaces between the first dielectric and between the conductive features, followed by the first dielectric features being removed. Second polymer layers are then formed over the second dielectric features, such that portions of the second polymer layers cover corresponding portions of the conductive features that are adjacent to the second dielectric features. Subsequently, the second polymer layers are used to pattern the conductive features, to thereby remove portions of the conductive features that are not covered by the polymer layers and define second conductive features. The first and second polymer layers can be formed using dielectric resolution enhancement coating techniques.

Method for reducing pitch

A method for pulling back SiN to increase rounding effect in a shallow trench isolation process, includes the steps of preparing a substrate of Si and forming a SiO layer on the substrate, forming a Si N layer on the SiO layer, defining Si N trenches by plasma etching, etching the remaining Si N with SF /HB gas, etching SiO layer to form a platform and enhance the rounding of the platform, etching the substrate to have a third shallow trench and a reinforced platform, filling the third shallow trench with oxide, planarizing the filled oxide using chemical mechanical polishing, and removing the Si N layer, wherein after the removal of the Si N layer, multiple cleaning processes are performed.

Method of rounding a topcorner of trench

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Hsinchu, Taiwan

Chia-Chi Chung