Chang Gung University

Chia-Chi Chu

Wu-Shiung Feng

Herng-Jer Lee

Ming-Hong Lai

Chao-Kai Chang

Sheng-Huei Lee

Hung-Chi Tsai

Chao-Yi Cho

Chia-Ming Ho

Chung-Hsiung Chen

Chao-Hsuan Hsu

This invention presents a method of novel nonlinear control for designing Static Synchronous Compensators (STATCOM). A passivity-based approach is proposed for designing robust nonlinear STATCOM controller. The mathematical model of STATCOM will be represented by an Euler-Lagrange (EL) system corresponding to a set of EL parameters. By employing the Park's transformation, the differential geometry approach is used to investigate the power system dynamics with considering STATCOM under the synchronous d-q frame. The energy-dissipative properties of the proposed model derived in the synchronous d-q rotating frame are fully retained. This model also consider the dynamic response of the changable load. Finally, the passivity-based control is employed by using energy shaping and damping injection techniques to produce the proper control signals for Voltage Source Converter. So that the system embedded with STATCOM is more robust and stable.

Method of designing a static synchronous compensator based on passivity-based control

A method to incorporate the steady-state model of the generalized power flow controller into a Newton-Raphson power flow algorithm adopts a flexible steady-state model of the generalized power flow controller, which can be applied to calculate the power flow solution of a power grid embedded with STATCOM, UPFC, GUPFC and the generalized power flow controller in a single framework. The method only incorporates the control variables of the shunt voltage sourced converter into the state vector of the Newton-Raphson power flow algorithm. The increment of the state variables due to incorporating the generalized power flow controller is less than the prior art. Further, the method can preserve the quadratic convergence characteristic of the Newton-Raphson power flow algorithm after embedding the generalized power flow controller into a power grid.

Method of calculating power flow solution of a power grid that includes generalized power flow controllers

The adjoint network reduction technique has been shown to reduce 50% of the computational complexity of constructing the congruence transformation matrix. The method was suitable for analyzing the special multi-port driving-point impedance of RLC interconnect circuits. This technique is extended for the general circumstances of RLC interconnects. Comparative studies among the conventional methods and the proposed methods are also investigated. Experimental results will demonstrate the accuracy and the efficiency of the proposed method.

Generalizations of adjoint networks techniques for RLC interconnects model-order reductions

A method estimates the signal delay in a VLSI circuit and accurately estimates the delay and conversion time of a transmission signal in the circuit in order to prevent a designer of the VLSI circuit from erroneously judging the logic made by the designed circuit.

Method of estimating the signal delay in a VLSI circuit

A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function is used to analyze an ideal value of skew and an error between feasible solutions. During operation, several algorithms are used to speed up the operation and lower the complexity, and ISCAS'89 is used as a testing circuit.

Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization

A model reduction method utilizing the rational Arnoldi method with adaptive orders (RAMAO) is applied to high-speed VLSI interconnect models. The method is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. Given a set of predetermined expansion points, an exact expression for the error between the output moment of the original system and that of the reduced-order system, related to each expansion point, is derived first. In each iteration of the proposed RAMAO algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. Hence, the corresponding reduced-order model yields the greatest improvement in output moments among all reduced-order models of the same order.

Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive orders

Two-sided projection-based model reductions have become a necessity for efficient interconnect modeling and simulations in VLSI design. In order to choose the order of the reduced system that can really reflect the essential dynamics of the original interconnect, the element of reduced model of the transfer function can be considered as a stopping criteria to terminate the non-symmetric Lanczos iteration process. Furthermore, the approximate transfer function can also be expressed as the original interconnect model with some additive perturbations. The perturbation matrix only involves at most a rank-2 modification at the previous step of the non-symmetric algorithm. The information of stopping criteria will provide a guideline for the order selection scheme used in the Lanczos model-order reduction algorithm.

Method of determining high-speed VLSI reduced-order interconnect by non-symmetric lanczos algorithm

An interconnect model-order reduction method reduces a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select an order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, with analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm. Therefore, the residual error information may be taken as a reference for the order selection scheme used in Krylov subspace model-order algorithm.

Interconnect model-order reduction method

A method of searching paths that are susceptible to electrostatic discharge (ESD) at the beginning of an integrated circuit (IC) design is disclosed that includes a circuit spreading out algorithm, a matrix closure algorithm, and a supernode algorithm. The found paths are required to satisfy conditions including that (a) they are connected from a gate of a transistor to a source or a drain thereof, and (b) the head node and the tail node of each path are pins of a top level of the IC. &#x2212;1/0/1 matrix multiplication is employed by both the circuit spreading out algorithm and the matrix closure algorithm so as to obtain a result of node connections after a plurality of matrix self-multiplications.

Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design

A method and apparatus for designing low-order linear-phase IIR filters is disclosed. Given an FIR filter, the method utilizes a new Krylov subspace projection method, called the rational Arnoldi method with adaptive orders, to synthesize an approximated IIR filter with small orders. The method is efficient in terms of computational complexity. The synthesized IIR filter can truly reflect essential dynamical features of the original FIR filter and indeed satisfies the design specifications. In particular, the linear-phase property is stilled remained in the passband.

Efficient digital filter design tool for approximating an FIR filter with a low-order linear-phase IIR filter

Power flow models of Interline Power Flow Controllers (IPFC) for large-scale power systems are studied, in details. Mathematical models of the IPFC, using the d-q axis decompositions of control parameters are derived. In this framework, for each IPFC, only two control parameters are added to the unknown vector in the iteration formula and the quadratic convergence characteristic is preserved. Simulations results from several practical large-scale power systems embedded with multiple Convertible Static Compensators (CSCs) demonstrate the effectiveness of the proposed models. Comparisons with existing models are made to elucidate the performance of the convergence.

Method for calculating power flow solution of a power transmission network that includes interline power flow controller (IPFC)

A moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each free and the corresponding links can be determined independently. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments efficiently. Experimental results demonstrate that the proposed method can indeed obtain accurate moments and is more efficient than the conventional approach.

Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops

A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. A developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both specifying database constrains and clock skew constrains. For a given clock tree netlist, location information of buffers, parameters of wires and buffers' timing and power library are all included. Buffer delay and wire delay of the given clock tree netlist are calculated first. Then, a feasible solution is solved if an input netlist is not feasible for given constrains. Finally, a modified low power clock tree netlist, which satisfies timing specifications, is obtained using the proposed method.

Clock tree synthesis for low power consumption and low clock skew

Computer time for modeling VLSI interconnection circuits is reduced by using symmetric properties of modified nodal analysis formulation. The modeling uses modified nodal analysis matrices then applies a Krylov subspace matrix to construct a congruence transformation matrix to generate the reduced order model of the VLSI.

Method and apparatus for model-order reduction and sensitivity analysis

A method and apparatus for rapidly selecting types of buffers which are inserted in the clock tree for high-speed VLSI design is disclosed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure minimizing the clock delay and satisfying the clock skew constrains. Given the clock tree netlist, the inserted buffers location information, the wire electrical parameters and a buffers timing library, the components delay (buffer delay and wire delay) of the clock tree can be calculated first. Then, for each I/O pin, the path delay, the clock delay and the clock skew can be obtained. Finally, using the method, a modified clock tree netlist satisfying the timing specifications can be constructed.

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Tao-Yuan, Taiwan

Chia-Chi Chu