Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Cheng Chou

Chung-Chi Ko

Keng-Chu Lin

Tze-Liang Lee

Po-Cheng Shih

Shwang-Ming Jeng

Chen-Hua Douglas Yu

Tien-I Bao

Joung-Wei Liou

Chih-Chien Chi

Chen-Yuan Kao

Yao-Jen Chang

Kai-Shiang Kuo

Jun-Yi Ruan

Chih-Hao Chen

Kuang-Yuan Hsu

Ming-Chung Liang

Tzu-Li Lee

Chih-Hung Sun

Yung-Cheng Lu

Pei-Ren Jeng

Shing-Chyang Pan

Zhen-Cheng Wu

Mei-Ling Chen

Ching-Ya Wang

Hui-Chun Yang

Ting-Yu Shen

Shwang-Ming Cheng

Ming-Tsung Lee

A method of forming an interconnect structure includes the following steps. A first etching stop layer, a first dielectric layer, a second etching stop layer, an insert layer and a second dielectric layer are deposited over the second etching stop layer are deposited over a substrate. The second dielectric layer, the insert layer, the second etching stop layer, the first dielectric layer and the first etching stop layer are patterned thereby forming a trench opening and a via hole. A conductive feature is filled in the trench opening and the via hole thereby forming a conductive line in the second dielectric layer and the insert layer and a via in the first etching stop layer and the first dielectric layer. A material of the insert layer is different from the second dielectric layer and the second etching stop layer.

Interconnect structures of semiconductor device and methods of forming the same

A semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. The low-k dielectric layer is disposed over the substrate. The cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. The conductive layer is disposed in the cap layer and the low-k dielectric layer.

Damascene process using cap layer

An interconnect structure includes an etching stop layer, a dielectric layer and an insert layer and a conductive line. The insert layer is located between the etching stop layer and the dielectric layer. The conductive line extends through the dielectric layer, the insert layer, and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.

An interconnect structure includes an interconnect structure includes an etching stop layer; a dielectric layer and an insert layer on the etching stop layer, and a conductive feature in the dielectric layer, the insert layer and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.

Methods of forming interconnect structures of semiconductor device

A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Interconnect structure and method

A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.

Forming interconnect structure using plasma treated metal hard mask

A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.

Automatically adjusting baking process for low-k dielectric material

Interconnect structures and methods for forming the same are described. A method for forming an interconnect structure may include: forming a low-k dielectric layer over a substrate; forming an opening in the low-k dielectric layer; forming a conductor in the opening; forming a capping layer over the conductor; and forming an etch stop layer over the capping layer and the low-k dielectric layer, wherein the etch stop layer has a dielectric constant ranging from about 5.7 to about 6.8.

Interconnect structure and method for forming the same

Embodiments of the disclosure provide a method for forming a semiconductor device structure. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes applying a carbon-containing material over the dielectric layer. The method further includes irradiating the dielectric layer and the carbon-containing material with a light to repair the dielectric layer, and the light has a wavelength greater than about 450 nm.

Method for forming semiconductor device structure

A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.

Low-k interconnect structures with reduced RC delay

A Ultra-Violet (UV) treatment is performed on an exposed surface of a low-k dielectric layer and an exposed surface of a metal line. After the UV treatment, an organo-metallic soak process is performed on the exposed surface of the low-k dielectric layer and the exposed surface of the metal line. The organo-metallic soak process is performed using a process gas including a metal bonded to an organic group.

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Chia-Cheng Chou