Taiwan Semiconductor Manufacturing Comp. Ltd.

Siliconware Precision Industries Co., Ltd.

Faraday Technology Corporation

National Yang Ming Chiao Tung University

Other

Hi-max Innovation Co., Ltd.

TSMC Nanjing Company, Limited

Chia-Cheng Chen

Liang-Yin Chen

Huicheng Chang

Yee-Chia Yeo

Chun-Hung Wu

Yu-Cheng Pai

Su-Hao Liu

Kuo-Ju Chen

Chun-Hsien Lin

Shih-Chao Chiu

Wei-Chung Hsiao

Ming-Chen Sun

Tzu-Chieh Shen

Ching-Wei Wu

Chih-Kai Yang

Yu-Tien Shen

Wei-Ting Chien

Huai-Tei Yang

Lun-Kuang Tan

Wei-Ming You

Clement Hsingjen Wann

Liang-Gi Yao

Chang-Miao Liu

Chun-Yen Chang

Ya Hui Chang

Ching-Te Chuang

Wei-Chiang Shih

Syun-Ming Jang Jang

Ying-Lang Wang

Ming-Hsi Yeh

Wei Hwang

Kuo-Bin Huang

Xiong-Fei Yu

Chun-Neng Lin

Jui-Che Tsai

Hao-I Yang

Hui-Cheng Chang

Chia-Ling Chan

Po-Nan Yeh

U-Ting Chiu

Yu-Shih Wang

Meng-Shu Lin

Ru-Gun Liu

Yih Wang

Cheng Hung Lee

Chia-En Huang

Jyu-Horng Shieh

Yung-Sung Yen

Wei-Liang Lin

Jeff J Xu

Yi-Nien Su

Ming-Hung Chang

Fu-Tang Huang

Shu-Huei Suen

Ya-Wen Yeh

Kuang Ting Chen

Ta-Ming Kuan

Yi-Wei Lin

Ya-Hui Chang

Wei-Shuo Kao

Chia-Fong Chang

Chun-Liang Chen

Mao-Chih Hsia

Hsiang-Ming Chang

Chi-Rui Wu

Hsuan-Hao Mi

Kei-Wei Chen

Szu-Ying Chen

Chun-Feng Nieh

Li-Ting Wang

Wan-Yi Kao

Sen-Hong Syue

Ying-Chou Tsai

Fu-Ming Huang

Wen-Jung Tsai

Chi-Ching Ho

Don-Son Jiang

Shyh-Jye Jou

Tang-Kuei Chang

Ming-Hsien Tu

Shao-Tzu Tang

Ji Cui

Wei-Wei Liang

Kun-Ti Lee

Chien-Yu Lu

Yi-Chen Tseng

Ming-hung Chang

Hung-Yu Li

Cheng Kai Chang

Luping Kong

Jui-Feng Chen

Chia-Cheng Hsu

Yu-Che Liu

Tzu-Chieh Chen

Harn-Bor Yang

Yung-Wei Lin

Wade Wang

Rick Zheng

James Ma

A method of forming a semiconductor device includes etching trenches in a substrate to form fin structures, depositing a liner layer to line the trenches, filling the trenches with an insulating layer, performing an ion implantation process to the insulating layer, after performing the ion implantation process, recessing the insulating layer to form shallow trench isolation (STI) regions adjacent the fin structures, and forming a gate crossing the fin structures.

Formation method of shallow trench isolation

In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including integrated circuit dies; measuring a position of the wafer by measuring a position of an outer edge of the integrated circuit dies with a camera; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

Wafer positioning method and apparatus

A memory circuit includes a control circuit coupled to the word line driver circuit. The control circuit is configured to delay a leading or falling edge of a word line signal in response to at least a first clock signal. The control circuit includes a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal, and an adjustable delay circuit configured to adjust a delay between the second and third clock signal in response to the second clock signal and an enable signal. The third clock signal is a delayed version of the second clock signal. An amount of the delay between the second and third clock signal is based on a voltage difference between a first supply voltage having a first swing, and a second supply voltage having a second swing.

Memory circuit and method of operating same

A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.

System and method for multiple step directional patterning

A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

Method of forming a semiconductor device

A circuit includes an array including a plurality of memory cells; a driver operatively coupled to the array and configured to provide an access signal controlling an access to one or more of the plurality of memory cells; and a timing controller operatively coupled to the driver. The timing controller is configured to: receive a control signal; and in response to the control signal transitioning from a first logic state to a second logic state, adjust a pulse width of the access signal within a single clock cycle containing a first phase and a second phase, wherein the first phase includes reading a first data bit stored in a first one of the one or more memory cells and the second phase includes writing a second data bit into the first memory cell.

Memory circuits with dynamically adjustable pulse widths and methods for operating the same

A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.

Ion exposure method and apparatus

In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.

Semiconductor processing tool and method of using an embedded chamber

In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Method of manufacturing semiconductor devices

Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

Semiconductor device and method of manufacture

A circuit and method for establishing a balanced negative voltage to a near-end and far-end of a bitline having a plurality of memory cells connected to the bitline is disclosed. A MOS capacitor and a metal capacitor are connected in parallel. The MOS capacitor is connected to the near-end of the bitline through a first switch transistor. The metal capacitor is connected to the near-end of the bitline through the first switch transistor and the far end of the bitline through a second switch transistor. A falling negative boost voltage is applied to the MOS capacitor and the metal capacitor. When the switch transistors are turned on during a write operation, the MOS capacitor and the metal capacitor are both coupled to the voltage at the near-end and far-end and drive the voltage to approximately equal the boost voltage, thereby providing a balanced voltage to the bitline.

Balanced negative bitline voltage for a write assist circuit

A method of forming a semiconductor device includes forming a photoresist over a target layer, where the target layer includes a substrate. The photoresist is patterned to form a patterned photoresist. Scum remains between portions of the patterned photoresist. The substrate is tilted relative to a direction of propagation of an ion beam. An ion treatment is performed on the scum. A pattern of the patterned photoresist is transferred to the target layer.

Semiconductor structure and method of forming the same

A method for forming a semiconductor device is provided. The method for forming a semiconductor device is provided. The method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer; performing a directional ion bombardment process to the photoresist layer, such that a carbon atomic concentration in the photoresist layer is increased; and etching the target layer using the photoresist layer as an etch mask.

Method for fabricating semiconductor device

The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Doping for semiconductor device with conductive feature

Growing community of inventors

Hsinchu, Taiwan

Chia-Cheng Chen