Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Cheng Chao

Sung-En Lin

Chun-Kuang Chen

Chung-Cheng Wang

Hsin-Chieh Huang

Chung-Ting Ko

Yuan-Ching Peng

Kuo-Yi Chao

Jiun-Ming Kuo

Yu-Wen Wang

Chih-Chung Chang

Yi-Hsiu Liu

You-Ting Lin

Jen-Hong Chang

Chun-Yu Kao

A semiconductor device includes a first channel structure extending along a first lateral direction and a second channel structure extending along the first lateral direction. The second channel structure is spaced apart from the first channel structure. The semiconductor device further includes a high-k dielectric structure extending along the first lateral direction and disposed between the first and second channel structures. The high-k dielectric structure has a bottom surface that comprises a bottommost portion and at least a first plateau portion elevated from the bottommost portion.

Semiconductor devices and methods of manufacturing thereof

Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.

Dielectric isolation structure for multi-gate transistors

A test wafer is placed inside a baking module and is baked. Via one or more temperature sensors, a cumulative heat amount delivered to the test wafer during the baking is measured. The measured cumulative heat amount is compared with a predefined cumulative heat amount threshold. In response to the comparing indicating that the measured cumulative heat amount is within the predefined cumulative heat amount threshold, it is determined that the baking module is qualified for actual semiconductor fabrication. In response to the comparing indicating that the measured cumulative heat amount is outside of the predefined cumulative heat amount threshold, it is determined that the baking module is not qualified for actual semiconductor fabrication.

Using cumulative heat amount data to qualify hot plate used for post-exposure baking

A method for fabricating a semiconductor device includes forming a fin structure that includes a plurality of semiconductor channel layers alternatively spaced apart from one another with a plurality of semiconductor sacrificial layers. The method further includes forming a semiconductor cladding layer extending along sidewalls of the fin structure. The method further includes patterning the semiconductor cladding layer to have a top surface with a highest point and a lowest point by performing at least one sequential combination of a first etching process and a second etching process. A vertical difference between the highest point and the lowest point is less than 3 nanometers.

A method includes depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming first spacers on the first mandrel and second spacers on the second mandrel; and selectively removing the second spacers while masking the first spacers. Masking the first spacers comprising covering the first spacers with a second mask and a capping layer over the second mask, and the capping layer comprises carbon. The method further includes patterning the first mask and transferring a pattern of the first mask to the target layer. Patterning the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacers.

Patterning semiconductor devices and structures resulting therefrom

A manufacturing method of a semiconductor device includes forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, where a topmost layer of the stack is one of the second semiconductor layers; forming a patterned mask layer on the topmost layer of the stack; forming a trench in the stack based on the patterned mask layer to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure; and removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, where the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.

Semiconductor device and manufacturing method thereof

Implementations described herein provide a method of forming a semiconductor device. The method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. The method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. The method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. The method further includes removing a top portion of the cladding structure. The method further includes removing the second hard mask layer after removing the top portion of the cladding structure.

Nanostructure and manufacturing method thereof

A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.

Semiconductor device and methods of forming the same

Using cumulative heat amount data to qualify hot plate used for postexposure baking

In a pattern forming method, a resist layer disposed on a wafer is exposed by an energy beam. A post-exposure-bake (PEB) is performed on the wafer with the exposed resist layer by using a PEB apparatus. After the PEB, the exposed resist layer is developed, thereby forming a resist pattern. The PEB apparatus includes a baking plate, and the wafer is placed on the baking plate for the PEB when a temperature of the wafer is within a predetermined temperature range.

Pattern forming method and apparatus for lithography

A dispensing head for dispensing a developer onto a substrate is provided. The dispensing head includes a housing configured to receive the developer. The dispensing head further includes at least one liquid outlet provided on the housing. The liquid outlet is configured to spray the developer onto an elongated area on the substrate. Also, the liquid outlet is configured to spray the developer along a dispensing direction that is tilted with respect to the normal direction of the substrate and perpendicular to the long-axis direction of the elongated area.

Growing community of inventors

Hsinchu, Taiwan

Chia-Cheng Chao