United Microelectronics Corp.

Chia-Chen Sun

Sheng-Yuan Hsueh

En-Chiuan Liou

Yu-Cheng Tung

Shih-Chieh Hsu

Yi-Chung Sheng

Yao-Chang Wang

Chung-Chih Hung

Yung-Teng Tsai

Song-Yi Lin

Sheng-Chieh Chen

Hung-Chin Lin

Chih-Yu Wu

Jun-Ming Chen

Chih-Kai Kang

Chi-Horn Pai

Po-Kuang Hsieh

Shu-Hsuan Chih

Po-Cheng Huang

Yi-Wen Chen

Po-Jui Liao

Jie-Ning Yang

Chi-Sheng Tseng

Kuang-Hung Huang

Shih-Chang Chang

Chang-Yih Chen

Fan-Wei Lin

Fan Wei Lin

A photomask structure having a first region and a second region is provided. The layout pattern density of the first region is smaller than the layout pattern density of the second region. The photomask structure includes a first layout pattern, a second layout pattern, and first assist patterns. The first layout pattern is located in the first region and the second region. The second layout pattern is located in the second region. The second layout pattern is located on one side of the first layout pattern. The first assist patterns are located on the first sidewall of the first layout pattern and separated from each other. The first sidewall is adjacent to the second layout pattern. The first assist patterns are adjacent to a boundary between the first region and the second region. The lengths of two adjacent first assist patterns decrease in the direction away from the boundary.

Photomask structure

A method for fabricating a static random access memory (SRAM) includes the steps of forming a first fin-shaped structure for a first pull-down (PD) transistor on a substrate, forming a second fin-shaped structure for a second PD transistor on the substrate, forming a third fin-shaped structure for a first pass gate (PG) transistor on the substrate, and forming a fourth fin-shaped structure for a second PG transistor on the substrate. Preferably, the first fin-shaped structure and the second fin-shaped structure include a first recess therebetween and the third fin-shaped structure and the fourth fin-shaped structure include no recess therebetween.

Static random access memory and method for fabricating the same

A method includes providing a layout pattern to a computer system. The layout pattern includes a first pattern, a second pattern, and a third pattern. A central line defined by connecting a line end of the second pattern and a line end of the third pattern overlaps with a middle portion of the first pattern. An optical proximity correction (OPC) is performed on the layout pattern to form a first auxiliary pattern. The first auxiliary pattern includes a first stripe pattern and a second stripe pattern both extending from the line end of the second pattern. The second stripe pattern is closer to the first pattern than the first stripe pattern, and an extending length of the second stripe pattern is less than an extending length of the first stripe pattern. The layout pattern and the first auxiliary pattern are outputted through the computer system onto a photomask.

Method of forming a layout pattern and photomask

A photomask structure including a layout pattern and at least one assist pattern is provided. The layout pattern includes corners. The assist pattern wraps at least one of the corners. There is a gap between the edge of the layout pattern and the assist pattern.

Provided is a semiconductor structure including a first and a second conductive layers, and a first group of vias. The second conductive layer is disposed on the first conductive layer. The first group of vias is disposed between and connects the first and the second conductive layer. The first group of vias includes a first, a second, a third and a fourth vias. The first and second vias are arranged in a first column. The third and fourth vias are arranged in a second column. The first via is adjacent to the third via. The second via is adjacent to the fourth via. The extension directions of the first and second vias are orthogonal to each other, the extension directions of the third and the fourth vias are orthogonal to each other, and the extending directions of the first and the third vias are orthogonal to each other.

Semiconductor structure

A die seal ring structure includes a metal interconnect structure on a substrate, in which the metal interconnect structure includes an inter-metal dielectric (IMD) layer on the substrate and a first metal interconnection disposed in the IMD layer. Preferably, a first side of the first metal interconnection includes a comb-shape portion in a top view, a second side of the first metal interconnection includes a linear line, a third side of the first metal interconnection includes a linear line, and a fourth side of the first metal interconnection includes a linear line.

Die seal ring structure

An interconnect for physically unclonable function (PUF), comprised of multiple arranged PUF cells. Each PUF cell includes at least two L-shaped metal line, wherein each L-shaped metal line includes a first part and a second part and is adjacent to a dummy metal line, and the first part of one L-shaped metal line is electrically connected to adjacent second part of another L-shaped metal line through via in vertical direction.

Interconnects for physically unclonable function and method of achieving physically unclonable function through interconnects

A method for fabricating a semiconductor device includes the steps of first forming an active device having a gate structure and a source/drain region on a substrate, forming an interlayer dielectric (ILD) layer on the active device, removing part of the ILD layer to form a contact hole on the active device without exposing the active device and the bottom surface of the contact hole is higher than a top surface of the gate structure, and then forming a metal layer in the contact holt to form a floating contact plug.

Semiconductor device and method for fabricating the same

A method for correcting a mask pattern includes: providing an original mask pattern including at least one dense pattern area and at least one isolated pattern area, and the original mask pattern being divided into a first pattern and a second pattern, wherein the first pattern is formed in the isolated pattern area and extends to the dense pattern area, and the second pattern is formed in the dense pattern area; forming at least one slot on at least one section of the first pattern, and the at least one section of the first pattern is located on at least one transition area between the at least one isolated pattern area and the at least one dense pattern area; and performing an optical proximity correction operation on the first pattern formed with at least one slot and the second pattern. Using the corrected mask pattern may avoid the occurrence of necking or breaking on portion of the post-transfer pattern.

Method for correcting mask pattern and mask pattern thereof

A mask includes a substrate, a main pattern, a first assist pattern, and a second assist pattern. The main pattern is disposed on the substrate. The main pattern includes a first pattern and second patterns. Two of the second patterns are disposed at two opposite sides of the first pattern in a first direction. The first assist pattern is disposed on the substrate and disposed in the main pattern. The second assist pattern is disposed on the substrate and disposed outside the main pattern. The first assist pattern disposed in the main pattern may be used to improve the pattern transferring performance in a photolithography process using the mask.

Mask and method of forming pattern

The present invention provides an alignment mark, the alignment mark includes at least one dummy mark pattern in a first layer comprises a plurality of dummy mark units arranged along a first direction, and at least one first mark pattern located in a second layer disposed above the first layer, the first mark pattern comprises a plurality of first mark units, each of the first mark units being arranged in a first direction. When viewed in a top view, the first mark pattern completely covers the dummy mark pattern, and the size of each dummy mark unit is smaller than each first mark unit. In addition, each dummy mark unit of the dummy mark pattern has a first width, each first mark unit of the first mark pattern has a second width, and the first width is smaller than half of the second width.

Alignment mark and measurement method thereof

A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.

A method for a semiconductor layout pattern decomposition includes following steps. (a) receiving a semiconductor layout pattern; (b) performing a first separation/decomposition to the semiconductor layout pattern to obtain a grille pattern and a non-grille pattern; (c) recognizing a plurality of intersection regions in the grille pattern and alternately marking the intersection regions with a first region and a second region; (d) performing a second separation/decomposition to the grille pattern to obtain a plurality of first sub-patterns and a plurality of second sub-patterns perpendicular to each other, the first sub-patterns including the first regions, the second sub-patterns including the second regions; and (e) introducing a plurality of first assistance features on the first regions in the first sub-patterns and on the second regions on the second regions in the second sub-patterns, respectively. The step (a) to the step (e) are implemented using a computer.

Growing community of inventors

Kaohsiung, Taiwan

Chia-Chen Sun