Industrial Technology Research Institute

Delta Electronics, Inc.

Chia-Chang Hsu

Ruey-Liang Ma

Jing-Shyang Hwu

Pei-Chuan Tsai

Po-Chun Kang

Kun-Cheng Wu

Sheng-Jian Chen

Cheng-Yi Lo

Chung-Chih Chang

Huei-Ru Tseng

Chien-kuo Tien

Shisheng Shang

Ping-Ta Tsai

Ming-Wei Chou

Zong-Jin Chuang

Chien-Kuo Tien

Wei-ting Chen

Lo-Chuan Hu

A power supply with duty cycle limiting circuit includes a conversion circuit, a drive circuit, a control unit, and a duty cycle limiting circuit. The duty cycle limiting circuit converts a control signal into a control voltage, and determines whether a power switch of a power supply is turned off according to the control voltage and a threshold voltage to limit a duty cycle of the power switch.

Power supply with duty cycle limiting circuit, duty cycle limiting circuit, and method of operating the same

A DC uninterruptible power supply apparatus with bidirectional protection function receives a DC power source and supplies power to a DC load. The DC uninterruptible power supply apparatus includes a first loop, a second loop, a third loop, and a control unit. The first loop receives the DC power source and supplies power to the DC load. The second loop converts the DC power source into an energy-storing power source to charge an energy-storing unit. The energy-storing unit provides a backup power source to the DC load through the third loop and the first loop. The control unit controls the first loop, the second loop, and the third loop to correspondingly provide a first protection mechanism, a second protection mechanism, and a third protection mechanism.

DC uninterruptible power supply apparatus with bidirectional protection function

A security certificate management method for a vehicular network node is applied in a vehicular network. A message is received. Whether a certificate in the message is revoked is determined. If the certificate in the message is revoked, a regional certificate revocation list (RCRL) is generated or updated based on the revoked certificate by the vehicular network node, and the RCRL is transmitted into a communication range of the vehicular network node.

Security certificate management method for a vehicular network node and vehicular network node applying the same

A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed. The fetcher also generates a search address for output to the branch target buffer. In response to the branch target buffer detecting a taken branch that crosses multiple cache blocks, the fetch address is increased so that it points to the next cache block to be fetched but the search address is maintained the same.

System for packing variable length instructions into fixed length blocks

Branch prediction and fetch mechanism for variable length instruction,

A data processing system for decoding instructions in parallel in a superscalar, complex instruction set computing (CISC) computer. In a training mode of operation, an encrypter 29 encrypts preprocessed instructions retrieved from an instruction cache 26. In a processing mode of operation, instruction information is fetched and decrypted in decrypter 30. A prefetcher 21 separates the fetched instruction according to the decrypted boundary information. An instruction length verifier 25 verifies that the instructions were separated correctly and controls decoders 22a-c according to the verification. If the verification is correct for a given set of instructions, the system processes the instructions in parallel through the decoders to a dispatch logic circuit 23 and then to functional units 24. If the verification is incorrect, those related instructions may be needed to decode serially.

Encrypting and decrypting instruction boundaries of instructions in a

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Taoyuan, Taiwan

Chia-Chang Hsu