Taiwan Semiconductor Manufacturing Comp. Ltd.

Chi-Yu Lu

Hui-Zhong Zhuang

Ting-Wei Chiang

Jung-Chan Yang

Li-Chun Tien

Chih-Liang Chen

Pin-Dai Sue

Po-Hsiang Huang

Fong-yuan Chang

Ni-Wan Fan

Lee-Chung Lu

Chih-Yu Lai

Hsiang-Jen Tseng

Cheng-I Huang

Chi-Lin Liu

Jerry Chang-Jui Kao

Zhe-Wei Jiang

Cheok-Kei Lei

Yi-Kan Cheng

Chin-Chou Liu

Yi-Hsin Ko

Sheng-Hsiung Chen

Shang-Hsuan Chiu

Ching-Wei Tsai

Jerry Chang Jui Kao

Shang-Wen Chang

Shang-Syuan Ciou

Mao-Wei Chiu

Stefan Rusu

Shang-Chih Hsieh

Meng-Hung Shen

Lipen Yuan

Wei-Ling Chang

Jung-Chou Tsai

Yu-Chi Li

Chia-Wei Tseng

Yu-Ti Su

Yen-Hung Lin

Meng-Kai Hsu

Wei-Hsiang Ma

Jiun-Jia Huang

Tommy Hu

Guo-Huei Wu

Ho Che Yu

Jyun-Hao Chang

Ya-Chi Chou

Jung-chan Yang

Ting-Yu Chen

Jeo-Yen Lee

Fei Fan Duan

Shih-Ming Chang

Xiangdong Chen

Ping-Wei Wang

Kuo-Nan Yang

Ken-Hsien Hsieh

Chia-Tien Wu

Feng-Ming Chang

Yi-Hsun Chiu

Chin-Shen Lin

Sheng-Hsiung Wang

Yung-Chen Chien

Wan-Yu Lo

Chung-Hsing Wang

Jian-Sing Li

Kuang-Ching Chang

Ruey-Wen Chang

Johnny Chiahao Li

Metallization structure for an integrated circuit. In one embodiment, an integrated circuit includes a metal-to-diffusion (MD) layer disposed over an active region of a cell, gates disposed over the active region of the cell, and a first metallization layer including M0 tracks disposed over the MD layer and the gates. The integrated circuit further includes a second metallization layer including M1 tracks disposed over the first metallization layer. The M1 tracks include first M1 tracks each having a first predetermined distance from an edge of the cell and second M1 tracks each having a second predetermined distance from the edge of the cell, wherein the first M1 tracks are longer than the second M1 tracks.

Semiconductor metal layer structure over cell region

A semiconductor device includes first and second active regions extending in parallel in a substrate, a plurality of conductive patterns, each conductive pattern of the plurality of conductive patterns extending on the substrate across each of the first and second active regions, and a plurality of metal lines, each metal line of the plurality of metal lines overlying and extending across each of the first and second active regions. Each conductive pattern of the plurality of conductive patterns is electrically connected in parallel with each metal line of the plurality of metal lines.

Semiconductor device including parallel configuration

A method of making an integrated circuit includes steps of selecting a first cell and a second cell for an integrated circuit layout from a cell library in an electronic design automation (EDA) system, the first and second cells each having a cell active area, a cell gate electrode, at least one fin of a first set of fins, and a cell border region, each cell also having the active area at an exposed side, and placing the first exposed side against the second exposed side at a cell border. The method also includes operations of aligning at least one fin of the first set of fins with at least one fin of the second set of fins across a cell border.

Integrated circuit having fins crossing cell boundary

An integrated circuit (IC) structure includes two active areas extending in a first direction, two gate structures extending in a second direction, a first metal segment extending in the second direction in a first metal layer, second and third metal segments extending in the first direction in a second metal layer, and a gate via structure extending from the third metal segment to one of the gate structures. The gate structures overlie the active areas, the first metal segment overlies each of the active areas between the gate structures, the second metal segment overlies a first active area and overlies and is electrically connected to the first metal segment, and the first and second metal segments are electrically connected to the second active area, isolated from the first active area between the gate structures, and connected to the first active area outside the gate structures.

First metal structure, layout, and method

An integrated circuit structure includes a first and second power rail on a first level, a first and second set of conductive structures on a second level and a first, second and third conductive structure on a third level. The first set of conductive structures is over the first power rail. The second set of conductive structures is over the second power rail. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and a first conductive structure of the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and a second conductive structure of the second set of conductive structures. The third conductive structure overlaps a third conductive structure of the first set of conductive structures and a third conductive structure of the second set of conductive structures.

Integrated circuit, system for and method of forming an integrated circuit

A semiconductor device includes a substrate. The semiconductor device further includes a first gate structure on a first side of the substrate. The semiconductor device further includes a second gate structure on a second side of the substrate, wherein the first side is opposite the second side. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

Method of making amphi-FET structure and method of designing

Semiconductor structures and methods for forming a semiconductor structure are provided. The method includes forming a first active semiconductor region disposed in a first vertical level of the semiconductor structure, forming a second active semiconductor region disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction, forming a first conductive structure disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.

Semiconductor structures and methods of forming the same

An integrated circuit includes a first conductor segment intersecting a first active-region structure at a source/drain region and a second conductor segment intersecting a second active-region structure at a source/drain region. The first conductor segment and the second conductor segment are separated at proximal edges by a separation distance. A distance from a first horizontal cell boundary to a proximal edge of the first conductor segment is larger than a distance from a second horizontal cell boundary to a proximal edge of the second conductor segment by a predetermined distance that is a fraction of the separation distance.

Arrangement of source or drain conductors of transistor

A semiconductor device includes a plurality of active regions extending in a first direction. The semiconductor device further includes a gate electrode over the plurality of active regions, wherein the gate electrode extends in a second direction perpendicular to the first direction. The semiconductor device further includes a power rail extending in the first direction. The power rail includes a first power rail portion adjacent to the first boundary, wherein the first power rail portion has a first inner edge, and a second power rail portion adjacent to the second boundary, wherein the second power rail portion has a second inner edge, and the first inner edge is offset from the second inner edge in the second direction.

Semiconductor device having power rail with non-linear edge

A method is provided, and including operations as below: forming multiple active areas extending in a first direction; forming multiple conductive patterns extending in a second direction different from the first direction and arranged in a first layer above the active areas; forming multiple gates extending parallel to the conductive patterns; and forming a first set of conductive lines extending in the first direction and arranged in three first metal tracks that are in a second layer above the first layer, wherein one of the first set of conductive lines is arranged in a middle track of the three first metal tracks, coupled to one of the gates and overlap a first shallow trench region between two of the active areas.

Integrated circuit

A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.

Reduced area standard cell abutment configurations

A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Method and system for generating layout diagram including wiring arrangement

A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Method of making semiconductor device having self-aligned interconnect structure

A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Semiconductor structure and method for forming the same

A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

System and method for generating layout diagram including wiring arrangement

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New Taipei, Taiwan

Chi-Yu Lu