Taiwan Semiconductor Manufacturing Comp. Ltd.

Chi-Yu Lu

Hui-Zhong Zhuang

Ting-Wei Chiang

Jung-Chan Yang

Li-Chun Tien

Chih-Liang Chen

Pin-Dai Sue

Ni-Wan Fan

Po-Hsiang Huang

Fong-yuan Chang

Lee-Chung Lu

Hsiang-Jen Tseng

Chi-Lin Liu

Jerry Chang-Jui Kao

Cheng-I Huang

Zhe-Wei Jiang

Cheok-Kei Lei

Yi-Kan Cheng

Chin-Chou Liu

Chih-Yu Lai

Yi-Hsin Ko

Sheng-Hsiung Chen

Ching-Wei Tsai

Shang-Syuan Ciou

Mao-Wei Chiu

Shang-Chih Hsieh

Jerry Chang Jui Kao

Shang-Wen Chang

Meng-Hung Shen

Lipen Yuan

Wei-Ling Chang

Jung-Chou Tsai

Shang-Hsuan Chiu

Yu-Chi Li

Chia-Wei Tseng

Stefan Rusu

Yu-Ti Su

Yen-Hung Lin

Meng-Kai Hsu

Wei-Hsiang Ma

Jiun-Jia Huang

Tommy Hu

Guo-Huei Wu

Jyun-Hao Chang

Ho Che Yu

Jung-chan Yang

Ting-Yu Chen

Jeo-Yen Lee

Shih-Ming Chang

Xiangdong Chen

Ping-Wei Wang

Kuo-Nan Yang

Ken-Hsien Hsieh

Feng-Ming Chang

Yi-Hsun Chiu

Chin-Shen Lin

Sheng-Hsiung Wang

Yung-Chen Chien

Wan-Yu Lo

Chung-Hsing Wang

Ya-Chi Chou

Kuang-Ching Chang

Jian-Sing Li

Ruey-Wen Chang

Johnny Chiahao Li

Fei Fan Duan

A semiconductor device includes a substrate. The semiconductor device further includes a first gate structure on a first side of the substrate. The semiconductor device further includes a second gate structure on a second side of the substrate, wherein the first side is opposite the second side. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

Method of making amphi-FET structure and method of designing

Semiconductor structures and methods for forming a semiconductor structure are provided. The method includes forming a first active semiconductor region disposed in a first vertical level of the semiconductor structure, forming a second active semiconductor region disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction, forming a first conductive structure disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.

Semiconductor structures and methods of forming the same

An integrated circuit includes a first conductor segment intersecting a first active-region structure at a source/drain region and a second conductor segment intersecting a second active-region structure at a source/drain region. The first conductor segment and the second conductor segment are separated at proximal edges by a separation distance. A distance from a first horizontal cell boundary to a proximal edge of the first conductor segment is larger than a distance from a second horizontal cell boundary to a proximal edge of the second conductor segment by a predetermined distance that is a fraction of the separation distance.

Arrangement of source or drain conductors of transistor

A semiconductor device includes a plurality of active regions extending in a first direction. The semiconductor device further includes a gate electrode over the plurality of active regions, wherein the gate electrode extends in a second direction perpendicular to the first direction. The semiconductor device further includes a power rail extending in the first direction. The power rail includes a first power rail portion adjacent to the first boundary, wherein the first power rail portion has a first inner edge, and a second power rail portion adjacent to the second boundary, wherein the second power rail portion has a second inner edge, and the first inner edge is offset from the second inner edge in the second direction.

Semiconductor device having power rail with non-linear edge

A method is provided, and including operations as below: forming multiple active areas extending in a first direction; forming multiple conductive patterns extending in a second direction different from the first direction and arranged in a first layer above the active areas; forming multiple gates extending parallel to the conductive patterns; and forming a first set of conductive lines extending in the first direction and arranged in three first metal tracks that are in a second layer above the first layer, wherein one of the first set of conductive lines is arranged in a middle track of the three first metal tracks, coupled to one of the gates and overlap a first shallow trench region between two of the active areas.

Integrated circuit

A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.

Reduced area standard cell abutment configurations

A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Method and system for generating layout diagram including wiring arrangement

A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Method of making semiconductor device having self-aligned interconnect structure

A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Semiconductor structure and method for forming the same

A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

System and method for generating layout diagram including wiring arrangement

The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

Standard-cell layout structure with horn power and smart metal cut

Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate, a power switch, a first power mesh and a second power mesh. The power switch is formed over the front surface of the semiconductor substrate. The first power mesh is formed over the power switch and is directly connected to the first terminal of the power switch. The second power mesh is formed over the back surface of the semiconductor substrate and is directly connected to the second terminal of the power switch.

Semiconductor device including frontside power mesh and backside power mesh and manufacturing method thereof

A method of forming a semiconductor device, includes forming an active region; forming first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction, and correspondingly overlap and electrically couple to the active region; forming a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, overlaps at least the first MD contact structure and the third MD contact structures; forming a first via-to-MD (VD) structure over, and electrically coupled to, the first MD contact structure and the V2V rail; and forming a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and is electrically coupled to the first VD structure.

Method of making a semiconductor device with V2V rail

The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

Metal cut optimization for standard cells

An integrated circuit structure includes a first, second and third power rail extending in a first direction, a first, second and third set of conductive structures extending in the second direction, and being located at a second level, and a first, second and third conductive structure extending in the second direction, and being located at a third level. The first conductive structure overlaps a first conductive structure of the corresponding first, second and third set of conductive structures. The second conductive structure overlaps a second conductive structure of the corresponding first, second and third set of conductive structures. The third conductive structure overlaps a third conductive structure of the corresponding first, second and third set of conductive structures.

Integrated circuit, system for and method of forming an integrated circuit

Growing community of inventors

New Taipei, Taiwan

Chi-Yu Lu