Samsung Electronics Co., Ltd.

Chi-Wook Kim

Soo-Bong Chang

Jun-Hyung Kim

Ho-Sung Song

Sung-Min Seo

Young-Yong Byun

Han-Gyun Jung

A method of manufacturing a semiconductor chip from a wafer having a test architecture includes forming a plurality of dies on a wafer, each of the plurality of dies including a semiconductor device, forming at least two common pads commonly coupled to the dies, the at least two common pads being formed in a scribe lane, the scribe lane distinguishing the dies with respect to each other, and simultaneously testing the semiconductor devices at a wafer level, using the at least two common pads.

Test architecture of semiconductor device, test system, and method of testing semicondurctor devices at wafer level

In a boosted voltage generating circuit of a semiconductor memory device, an active kicker drive signal generating circuit generates an active kicker drive signal having a first pulse duration in response to a row active command, and generates the active kicker drive signal having a second pulse duration in response to a refresh command. An active kicker circuit is responsive to the active kicker drive signal to generate the boosted voltage. The second pulse duration may be greater than the first pulse duration, which makes it possible to improve the pumping efficiency of the boosted voltage in a refresh operation.

Circuit and method for generating boosted voltage in semiconductor memory device

A memory device includes a memory cell array block including memory cells, a word line driver block adjacent the memory cell array block disposed in a direction in which word lines of the memory cells are arranged, a sense amplifier block adjacent the memory cell array block disposed in a direction in which bit lines of the memory cells are arranged, a conjunction block disposed at an intersection of the word line driver block and the sense amplifier block, an equalizer for equalizing a pair of local data lines, the equalizer disposed in the conjunction block, and a local data line sense amplifier configured to sense and amplify signals on a pair of local data lines, and having transistors of a first type disposed in the conjunction block and transistors of a second type disposed in the sense amplifier block.

Layout for equalizer and data line sense amplifier employed in a high speed memory device

A redundancy repair circuit and method therefor for use with a semiconductor memory device are provided. The redundancy repair circuit comprises: a memory circuit having a plurality of address lines and a plurality of redundancy address lines in a memory cell; a repair redundancy control circuit for repairing a defective address line using a redundancy address line of the plurality of redundancy address lines, and for encoding and outputting fuse repair information corresponding to redundancy address information, wherein addresses corresponding to defective memory cells are pre-programmed; and a redundancy line driver for receiving the fuse repair information from the repair redundancy control circuit, for decoding the fuse repair information and for activating a redundancy line corresponding to the decoded fuse repair information, wherein the repair redundancy control circuit is separate from the redundancy line driver.

Redundancy repair circuit and a redundancy repair method therefor

A substrate voltage generating circuit for use in a semiconductor memory device is provided. The semiconductor memory device includes a charge pump for generating a substrate bias voltage in response to a clock signal; a first inverter type detector for detecting whether the substrate bias voltage reaches a target voltage; a second differential amplifier type detector for detecting whether the substrate bias voltage reaches the target voltage; and a driver for generating the clock signal in response to an output of one of the first and second detectors.

Growing community of inventors

Hwaseong-si, South Korea

Chi-Wook Kim