Intel Corporation

Chi-won Hwang

Yoshihiro Tomita

Sriram Muthukumar

Raul Mancera

Daewoong Suh

Devendra Natekar

A carbon nanotube solder is formed on a substrate of an integrated circuit package. The carbon nanotube solder exhibits high heat and electrical conductivities. The carbon nanotube solder is used as a solder microcap on a metal bump for communication between an integrated circuit device and external structures.

Carbon nanotube-reinforced solder caps, and chip packages and systems containing same

In one embodiment, a method includes forming a plurality of vias partially through a body, the vias including sidewalls defined by the body. An electrically insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. The body is thinned through a lower surface and the electrically insulating layer in the vias is exposed. After the thinning, a portion of the electrically insulating layer in the, vias is removed. The body is coupled to a substrate.

Methods for making multi-chip packaging using an interposer

Methods of forming microelectronic device structures are described. Those methods may include forming a passivation layer on a substrate, wherein the substrate comprises an array of conductive structures, forming a first via in the passivation layer, forming a second via in the passivation layer that exposes at least one of the conductive structures in the array, and wherein the second via is formed within the first via space to form a step via, and forming a conductive material in the step via, wherein a round dimple is formed in the conductive material.

Methods of forming C4 round dimple metal stud bumps for fine pitch packaging applications and structures formed thereby

The formation of electronic assemblies is described. One embodiment includes providing a body and forming a first metal pad layer on a first surface thereof. A second metal pad layer is formed in contact with the first metal pad layer, the second metal pad layer having a denser pitch than the first metal pad layer. A dielectric layer is formed between the metal pads in the first and second metal pad layers. Vias extending through the body from a second surface thereof are formed, the vias exposing the first metal pad layer. An insulating layer is formed on via sidewalls and on the second surface, and an electrically conductive layer formed on the insulating layer and on the exposed surface of the first metal layer. Elements are coupled to the second metal pad layer and the electrically conductive layer coupled to a substrate. Other embodiments are described and claimed.

Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias

One embodiment relates to forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body. An insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. A plurality of electronic elements are coupled to the second metal pads. After the coupling the elements, the body is thinned through a lower surface. A portion of the insulating layer in the vias is removed and the electrically conductive layer is coupled to a substrate.

Multi-chip packaging using an interposer with through-vias

A method of making a carbon nanotube reinforced solder cap. Carbon nanotube-solder (CNT-S) particles are transferred from a transfer substrate, having an adhesive layer, to a solder bump by using thermo compression bonding. The CNT-S particles are then reflowed to form a cap on the solder bump. The solder bump with the reflowed cap can then be joined to a bonding pad or another solder bump with a cap by placing the solder bump on the pad or other bump and reflowing at a temperature sufficient to reflow the cap(s).

Method of assembling carbon nanotube reinforced solder caps

A microelectronic cooling assembly and method for fabricating the same are described. In one example, a microelectronic cooling assembly includes a microelectronic device, a heat spreader, and a thermal interface material (TIM) that thermally joins the microelectronic device and heat spreader, the TIM comprising a sintered metallic nanopaste.

Sintered metallic thermal interface materials for microelectronic cooling assemblies

Horizontal carbon nanotubes may be used for on-die routing and other applications. In one example, a catalyst is applied to a plurality of different points on a substrate. Carbon nanotubes are then grown vertically on the plurality of different points to form a plurality of vertical carbon nanotube structures on the substrate. The vertical carbon nanotuhe structures are then rolled to form horizontal carbon nanotube structures.

Horizontal Carbon Nanotubes by Vertical Growth and Rolling

A method and apparatus including an interconnect structure having a surface, a plurality of nanotubes disposed adjacent to the surface, and a metallic layer disposed adjacent to the surface and substantially including the nanotubes. An assembly may include a first embodiment of an apparatus as described, and may further include a second such embodiment at least one of physically and electrically coupled to the first embodiment.

Growing community of inventors

Ibaraki, Japan

Chi-won Hwang