Samsung Electronics Co., Ltd.

Chi Weon Yoon

Sang-Wan Nam

Dong Hyuk Chae

Jung-Yun Yun

Donghyuk Chae

Jae-Woo Park

Sang Wan Nam

Dong Hun Kwak

Hyun Kook Park

Dae Seok Byeon

Yong Jun Lee

Chea Ouk Lim

Young Hoon Oh

Chan Kim

Jung Sunwoo

Tae-hong Kwon

Kyung Hwa Yun

Wan Dong Kim

Doo Ho Cho

Kyo Man Kang

Jung Ho Song

At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where 'k' is 2 or a natural number greater than 2.

Address scheduling methods for non-volatile memory devices with three- dimensional memory cell arrays

In order to permit dense integration of a high number of stacked word lines in the semiconductor memory device, a charge pump is included in the semiconductor memory device. The charge pump makes use of a capacitor. The capacitor is implemented with respect to the dense integration. Some components are placed under the stacked word lines, and some are not under the stacked word lines. The capacity of the capacitor not under the stacked word lines is provided in part by a parallel structure.

Semiconductor memory device with a plurality of amplification stages

Address scheduling methods for non-volatile memory devices with three-dimensional memory cell arrays

A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.

Memory device

A method for initializing a channel in a non-volatile memory device comprising a memory block including a plurality of word lines and a plurality of string selection lines, includes applying a voltage to the plurality of string selection lines; converting a bit line passing through the block into a floating state; and a releasing the floating state of the bit line.

Device and method for initializing channel in nonvolatile memory device

A resistive memory element or device includes: a first, main, memory cell area including a plurality of first resistive memory cells; and a second, buffer, memory cell area including a plurality of second resistive memory cells. The first resistive memory cells of the main memory cell area are configured to store data therein, and the second resistive memory cells of the buffer memory cell area are configured to temporarily store portions of the data therein for at least a stabilization time period while the portions of the data stabilize in the main memory cell area.

Memory device comprising resistance change material and method for driving the same

A memory device includes a first memory area, a second memory area, a third memory area and a controller. The first memory area has a plurality of first memory cells sharing a first channel area. The second memory area has a plurality of second memory cells sharing the first channel area. The third memory area having a plurality of third memory cells sharing a second channel area, the second channel area being different from the first channel area, the first channel area and the second channel area being connected to a bit line. The controller is configured to input a voltage for the second memory cells to the second memory cells and a voltage for the third memory cells to the third memory cells, when a controlling operation is performed on the first memory cells, the voltages for the second and third memory cells having different magnitudes.

Memory device with voltage controller

A memory device includes a memory cell array including a plurality of word lines, a first string select line above the plurality of word lines, and a second string select line between the first string select line and the plurality of word lines, and a controller. During an operation of reading data of a first memory cell connected to a first word line among the plurality of word lines, the controller is to supply a first voltage to the first string select line and to supply a second voltage to the second string select line, the second voltage being greater than the first voltage.

An operating method of a memory device is provided. Using a statistical model, a resistance Rof a variable resistor of a memory cell and a variation &#x394;Rof the resistance Rare determined. Based on the resistance Rand the variation &#x394;Rof the resistance R, an average resistance Rand a beta value of the variable resistor are determined. Then, using the average resistance Rand the beta value, a resistance Rof an insertion resistor, connected between the memory cell and a power supply generator for generating a power supply voltage V, is determined.

Operating method of memory device

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

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Seoul, South Korea

Chi Weon Yoon