Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Wistron Corporation

National Yang Ming Chiao Tung University

E Ink Holdings Inc.

Chi-Wen Chang

Jui-Feng Kuan

Yi-Kan Cheng

Hui Yu Lee

Ya Yun Liu

Hui-Yu Lee

Wen-Shen Chou

Yi-Pai Huang

Fang-Cheng Lin

Han-Ping D Shieh

Chin-Hua Wen

Yu-Tseng Hsien

Hsin-Tao Huang

Yu-Nan Pao

Sheng-Chieh Tai

Meng-Chao Kao

Hui-Chen Lin

Chih Ming Yang

Szu-Fen Chen

Kai-Tung Teng

A method of making a semiconductor device includes determining a first scaling factor for a first region of a first device layout, wherein the first region comprises a first plurality of conductive patterns. The method further includes determining a second scaling factor for a second region of the first device layout, wherein the second region comprises a second plurality of conductive patterns, and the first device layout comprises an interconnect pattern extending from the first region to the second region. The method further includes generating a second device layout. Generating the second device layout includes adjusting the interconnect pattern based on the first scaling factor and the second scaling factor.

Region based shrinking methodology for integrated circuit layout migration

A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

Structure and method for cooling three-dimensional integrated circuits

A method includes assigning a default voltage value to a net in an integrated circuit (IC) schematic, generating a simulation voltage value of the net by performing a circuit simulation on the net using the assigned default voltage value, and modifying the IC schematic to include a voltage value associated with the net. The voltage value associated with the net and included in the modified IC schematic is based on a comparison between the assigned default voltage value and the simulation voltage value of the net.

Integrated circuit design method, system and computer program product

A method of making a semiconductor device includes receiving a first layout of a device in a first technology node, wherein the first layout comprises a plurality of first conductive patterns spaced along a first direction and a plurality of first interconnect patterns connecting at least two of the plurality of first conductive patterns. The method includes identifying a plurality of second conductive patterns from the plurality of first conductive patterns according to a second technology node different from the first technology node. The method includes determining a scaling factor for the first layout in the first direction based on the plurality of first conductive patterns and the plurality of second conductive patterns. The method includes adjusting the plurality of first interconnect patterns along the first direction using the scaling factor to determine a plurality of second interconnect patterns connecting at least two of the plurality of second conductive patterns.

A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC), wherein the first die comprises a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions.

Method for making a semiconductor device

A display device includes a display panel, a light source module and a control unit. The display panel includes plural display areas. The light source module includes plural light source units. The light source units are configured to output plural light beams to illuminate the display areas of the display panel. The control unit is coupled to the light source module and configured to receive a frame data. The frame data includes plural subframe data, and the subframe data are displayed on the display areas. The control unit is further configured to control a first light source unit of the light source units to adjust a brightness corresponding to a first color of a first light beam of the light beams according to a ratio of the first color. The ratio of the first color is related to a first subframe data of the subframe data.

Display device

A method includes assigning a default voltage value of a voltage domain in an integrated circuit (IC) schematic to a net in the voltage domain, generating a simulation voltage value of the net by performing a circuit simulation on the net, and modifying the IC schematic to include a voltage value associated with the net, based on the simulation voltage value of the net.

A method of modifying an integrated circuit (IC) design layout is provided. The method includes receiving a first IC design layout having first gate layout patterns and first interconnect layout patterns. Second gate layout patterns for a second IC design layout are then obtained from the first gate layout patterns according to a set of design rules associated with a technology node different from that of the first IC design layout. After determining scaling factors for the first IC design layout based on the first gate layout patterns and the second gate layout patterns such that each scaling factor corresponds to one of at least one shrinkable region and at least one non-shrinkable region in the first IC design layout, the first interconnect layout patterns are adjusted using the scaling factors to determine second interconnect layout patterns for the second IC design layout.

A system including a memory; and a simulation tool connected to the memory. The simulation tool is configured to receive information related to a plurality of dies. The simulation tool is further configured to receive a plurality of input vectors. The simulation tool is further configured to determining a temperature profile for a first die of the plurality of dies. The simulation tool is further configured to simulate operation of a second die of the plurality of dies based on the determined temperature profile and the received plurality of input vectors.

System for manufacturing a semiconductor device

A color sequential image method for displaying images using two color fields includes analyzing and sorting percentages of a plurality of colors constituting an input color image, in which a first color possesses a most percentage, a second color possesses a middle percentage, and a third color possesses a third percentage. The method further includes forming a first color field image according to the first color and the third color, and a second color field image according to the second color and the third color.

Color sequential image method and system thereof

An apparatus includes a first tier and a second tier. The second tier is above the first tier. The first tier includes a first cell. The second tier includes a second cell and a third cell. The third cell includes a first inter layer via (ILV) to couple the first cell in the first tier to the second cell in the second tier. The third cell further includes a second ILV, the first ILV and the second ILV are extended along a first direction. The first tier further includes a fourth cell. The second tier further includes a fifth cell. The second ILV of the third cell is arranged to connect the fourth cell of the first tier with the fifth cell of the second tier. In some embodiments, the second tier further includes a spare cell including a spare ILV for engineering change order (ECO) purpose.

Method and apparatus of a three dimensional integrated circuit

A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC). The method further includes identifying a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions. The method further includes manufacturing the semiconductor device.

Method of manufacturing a semiconductor device

A display method and a display device are disclosed herein. The display method includes the following steps: analyzing an input image to obtain a plurality of first backlight control signals and a plurality of first liquid crystal control signals; generating image edge information associated with the input image; generating, according to the image edge information, at least one second backlight control signal and at least one target liquid crystal control signal that are associated with the image edge information; and displaying, according to the at least one second backlight control signal and the at least one target liquid crystal control signal, at least one multi-color sub-frame.

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Yuanlin, Taiwan

Chi-Wen Chang