Taiwan Semiconductor Manufacturing Comp. Ltd.

Chi Wei Hu

Chung-Hsing Wang

Chin-Chou Liu

Min-Yuan Tsai

Shu-Yi Ying

Mahantesh Hanchinal

Yuan-Te Hou

Yen-Hung Lin

Lee-Chung Lu

Nan-Hsin Tseng

Wei-Pin Changchien

Ji-Jan Chen

Myron O Shak

Wu-An Kuo

Kevin Hung

Saurabh Gupta

Kuo-Yin Chen

A method of manufacturing an integrated circuit includes adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first and second pair of conductive patterns on the corresponding first and second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and a second set of conductive structures based on the second pair of conductive patterns. A first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. One spacing of a first set of spacings is different from another spacing of the first set of spacings.

Method and layout of an integrated circuit

A method of manufacturing an integrated circuit includes generating a layout of a first and a second cell, adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first pair of conductive patterns on the first set of routing tracks, placing a second pair of conductive patterns on the second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and forming a second set of conductive structures based on the second pair of conductive patterns. The first and second cell have a same cell height that is a non-integer multiple of a minimum pitch.

A method of manufacturing an integrated circuit includes identifying a first cell of a layout, placing a first pair of conductive patterns on a first set of routing tracks, placing a second pair of conductive patterns on a second set of routing tracks, and forming, by a first mask, a first set of conductive structures based on the first pair or second pair of conductive patterns. The first cell abuts a second cell. The first cell has a first set of routing tracks. The second cell has a second set of routing tracks. The first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. A top and bottom boundary of the first cell overlaps a pair of the first set of routing tracks. A top and bottom boundary of the second cell overlaps a pair of the second set of routing tracks.

A method of designing a layout includes identifying a cell having a cell height being a non-integral multiple of a minimum pitch, generating, using a processor, possibilities of an ordered arrangement of a plurality of virtual grid lines parallel to the top boundary and the bottom boundary, and placing at least two conductive patterns on the plurality of virtual grid lines. The cell height is defined by a top boundary and a bottom boundary, and the minimum pitch is based on a manufacturing process. The plurality of virtual grid lines are separated from each other by a plurality of spacings, and the top boundary overlaps a first virtual grid line of the plurality of virtual grid lines and the bottom boundary overlaps a second virtual grid line of the plurality of virtual grid lines. At least one spacing is different from another spacing of the plurality of spacings.

A method is performed at least in part by at least one processor. In the method, a plurality of circuit elements are placed in a layout for a semiconductor device, the plurality of circuit elements having a plurality of pins. A layer assignment is generated to assign a plurality of interconnections to corresponding conductive layers of the semiconductor device, the plurality of interconnections connecting corresponding pairs of pins among the plurality of pins. The plurality of interconnections is routed in the layout in accordance with the layer assignment.

Method, system and computer program product for generating layout for semiconductor device

Among other things, one or more systems and techniques for tier based layer modification, such as promotion or demotion, for a design layout are provided herein. A metal scheme describes one or more metal layers of the design layout, which are grouped into a set of tiers based upon resistivity similarity between the metal layers. Wire segments of the design layout are evaluated for promotion to tiers providing improved performance, for demotion to tiers providing decreased performance so that relatively faster routing resources are freed up for other wire segments, or for modification such as widening of wire segments. Via count penalties corresponding to timing delays of additional vias used to reassign wire segments are taken into account during promotion. Routing resource gains associated with reassigning wire segments are taken into account during demotion. In this way, wire segments of the design layout are promoted, demoted, or modified.

Tier based layer promotion and demotion

A method of forming a semiconductor arrangement is provided. The semiconductor arrangement includes an interconnection arrangement comprising a first connection between a driver and a receiver. At least one buffer is disposed along the first connection to reduce delay associated with the interconnection arrangement. However, buffers increase power consumption, and thus a determination is made as to whether a buffer is unnecessary. A buffer is determined to be unnecessary where removal of the buffer does not violate a timing constraint regarding an amount of time a signal takes to go from the driver to the receiver. If a buffer is determined to be unnecessary, the buffer is removed to reduce power consumption.

Semiconductor arrangement formation

Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time.

Apparatus and method for on-chip sampling of dynamic IR voltage drop

A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module.

Growing community of inventors

Pingzhen, Taiwan

Chi Wei Hu