Mediatek Corporation

Chi-Ta Wu

Chien-Hung Lin

Shao-Yu Wang

Yu-Ting Kuo

ShengJe Hung

Meng-Hsuan Cheng

Tai-Lung Chen

Henrry Andrian

Yi-Siou Chen

An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.

Neural network engine with tile-based execution

Growing community of inventors

Hsinchu, Taiwan

Chi-Ta Wu