Taiwan Semiconductor Manufacturing Comp. Ltd.

Chi-Ta Lu

Chi-Ming Tsai

Wei-Chung Hu

Chih-Chiang Tu

Cheng-Ming Lin

Dong-Hsu Cheng

Peng-Ren Chen

Ching-Yueh Chen

Jia-Guei Jou

Yihung Lin

Ting-Chang Hsu

Yu-Tung Chen

Chia-Hui Liao

Huang-Ming Wu

Chang-Jyh Hsieh

Yi-Hsien Chen

Jiun-Hao Lin

Yi-Feng Lu

A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a second conductive line disposed adjacent to the first conductive line, surrounded by the dielectric layer and extended parallel to the first conductive line; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via substantially parallel to the first surface of the substrate, wherein the cross section of the conductive via is at least partially protruded from the first conductive line towards the second conductive line. Further, a method of manufacturing the semiconductor structure is also disclosed.

Semiconductor structure and manufacturing method thereof

A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

Critical dimension uniformity

A method for manufacturing a semiconductor device is provided. The method includes the following operations. A first layout including a plurality of first features is provided. A modified second layout is determined. The modified second layout includes a plurality of modified features separated from each other, and each of the plurality of modified features respectively overlaps each of the plurality of first features. The modified second layout is outputted to a photomask.

Method for manufacturing semiconductor device

A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Mask defect prevention

A method includes: receiving a design layout comprising a feature extending in a peripheral region and a central region of the design layout; determining compensation values associated with a pellicle assembly and the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout according to the compensation values. The modifying of the shape of the feature according to the compensation values includes: partitioning the peripheral region into compensation zones, wherein the feature includes first portions disposed within the respective compensation zones and a second portion disposed within the central region; and reducing line widths of the first portions of the feature according to the compensation values associated with the respective compensation zones while keep the second portion of the feature uncompensated.

Method and system for reducing layout distortion due to exposure non-uniformity

A method for manufacturing a semiconductor device is provided. The method includes providing a first layout including a plurality of first features and a second layout including a plurality of second features; shifting the second layout to generate a plurality of virtual layouts; comparing a score of each of the plurality of virtual layouts and determining a modified second layout having a target score out of the plurality of virtual layouts; and outputting the modified second layout to a photomask.

A method, a non-transitory computer-readable storage medium and a system for adjusting a design layout are provided. The method includes: receiving a design layout including a feature in a peripheral region of the design layout; determining a first compensation value associated with the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout by modifying a shape of the feature according to the compensation value.

Present disclosure provide a method for fabricating a mask, including obtaining a target pattern to be imaged onto a substrate, providing a first scattering bar and a second scattering bar adjacent to consecutive edges of the target pattern, identifying a first length of the first scattering bar and a second length of the second scattering bar, connecting the first scattering bar and the second scattering bar when any of the first length and the second length is smaller than a predetermined value, identifying a separation between the first scattering bar and the second scattering bar subsequent to identifying the first length and the second length, disposing the first scattering bar and the second scattering bar in a first fashion when the separation is equal to zero, and disposing the first scattering bar and the second scattering bar in a second fashion when the separation is greater than zero.

Mask and method for fabricating the same

A method of generating an integrated circuit includes: receiving, by a processor, a first IC design layout; replacing, by the processor, a specific region in the first IC design layout with a first difference region; performing, by the processor, an inverse lithography technology process upon a junction region between the first difference region and the first IC design layout to generate a mask data; and causing the IC to be fabricated according to the mask data.

Using inverse lithography technology in a method of mask data preparation for generating integrated circuit

A method for manufacturing a photomask is provided. The method includes generating a plurality of virtual layouts; calculating a score for each of the plurality of virtual layouts in accordance with a total overlay area; comparing the scores of the plurality of virtual layouts and determining a modified layout having a target score out of the plurality of virtual layouts; and outputting the modified layout to a photomask. Each of the virtual layouts includes a plurality of the shifted features. A semiconductor manufacturing method is also provided.

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Yilan County, Taiwan

Chi-Ta Lu