Samsung Electronics Co., Ltd.

Chi-sung Oh

Chul-Sung Park

Eunsung Seo

Sang-Bo Lee

Dong-hyun Sohn

Seok Ho Kim

Hyo-Joo Ahn

A semiconductor memory package includes a base layer that communicates with a memory controller; at least one memory layer that is stacked on the base layer; and at least one through silicon via that penetrates through the at least one memory layer, wherein at least one signal bump for exchanging a signal with the memory controller is disposed in a first area of the base layer located to be adjacent to the memory controller, and wherein the first area corresponds to an edge area of the base layer, and a power bump for receiving power from outside of the semiconductor memory package for performing a signal processing operation on the signal is disposed in a second area of the base layer contacting the at least one through silicon via, wherein the second area corresponds to an area other than edge areas of the base layer.

Semiconductor memory package including stacked layers and memory device and semiconductor memory system having the same

A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

Semiconducotr memory device including non-volatile memory cell array

A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.

Memory system having memory ranks and related tuning method

An output circuit and method thereof. In an example, the output circuit may include an output buffer configured to buffer output data and to transfer the buffered output data to an output node, the output buffer initializing the output node in response to a triggering signal. In another example, the method may include buffering output data in response to an output buffer enabling signal, transferring the buffered output data to an output node and initializing the output node of an output buffer in response to a triggering signal.

Growing community of inventors

Suwon-si, South Korea

Chi-sung Oh