National Applied Research Laboratories

National Chip Implementation Center National Applied Research Laboratories

National Chip Implementation Center

Chi-sheng Lin

Chien-Ming Wu

Chun-Ming Huang

Chi-Shi Chen

Shih-Lun Chen

Chen-Chia Chen

Chin-Long Wey

Chih-Chyau Yang

Ming-Der Shieh

Shih-Hao Fang

Shing-Chung Tang

A microparticle detecting apparatus is disclosed and includes at least one detection unit, each of which includes: a first sieve having at least a first mesh, a separator stacked on one side of the first sieve and having a separator hole, and a second sieve stacked on one side of the separator and having several second meshes. The diameter of the second mesh is smaller than that of the first mesh, and the first and second meshes are misaligned with each other in a vertical direction of the first and second sieves. The detection unit further includes at least a sensor aligned with the first or second mesh for detecting microparticles trapping into the first mesh or passing through the second mesh. Therefore, the microparticle detecting apparatus is suitably used for detecting or counting any microparticles with different size, to effectively shorten the detection processes of sample fluids.

Microparticle detecting apparatus

A miniature sieve apparatus is described and includes a first sieve, a separator and a second sieve from top to bottom. The first and second sieves are formed with at least one first mesh and a plurality of second meshes, respectively. The first and second meshes are misaligned with each other in a vertical direction of the first and second sieves. The miniature sieve apparatus is provided to separate or screen microparticles with different sizes, such as target cells, bio-medical particles, organic or inorganic microparticles. Additionally, the invention also provides a manufacturing method of the miniature sieve apparatus, and the same material is applied to manufacture the sieves and the separators. Thus, the problem caused by the residual thermal stress due to different material can be solved. Therefore, the cost of the miniature sieve apparatus can be lowered as the yield rate thereof is improved.

Miniature sieve apparatus and manufacturing method thereof

The present invention provides a method for manufacturing a modularized integrated circuit (IC). The method includes the following steps: providing a base; and coupling an input/output module with the base. The base includes a lead-frame and a first package. The first package covers the lead-frame but exposes first contact points. The input/output module includes a first substrate, a plurality of first conducting columns, and a plurality of third contact points. A portion of each of the third contact points is electrically connected to a corresponding one of the first contact points. The method enhances the flexibility of IC design, and reduces the time and costs of developing new process techniques.

Method for manufacturing modularized integrated circuit

A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

Three-dimensional SoC structure formed by stacking multiple chip modules

A method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder and a low-complexity LDPC decoder using the same method are provided. The main idea of the method for arranging memories of a low-complexity LDPC decoder is to merge at least one or two small-capacity memory blocks into one memory group, so that the memory area can be reduced and the power consumption in reading or writing data is lowered. Besides, as the merged memory group shares the same address line in reading or writing data, at least one delay unit is used to adjust the reading or writing order and thereby ensure data validity. A low-complexity LDPC decoder using the disclosed method can meet the demands of high processing rate and low power consumption.

Method for arranging memories of low-complexity LDPC decoder and low-complexity LDPC decoder using the same

A multi-layer system-on-chip (SoC) module structure is provided. The multi-layer SoC module structure includes at least two circuit board module layers and at least one connector module layer. Each connector module layer is sandwiched between and thus electrically connects two circuit board module layers such that the SoC module structure is formed by stacking. Each circuit board module layer is composed of at least one circuit board module while each connector module layer is composed of at least one connector module. Hence, the SoC module structure can be manufactured as a three-dimensional structure, thus allowing highly flexible connections within the SoC module structure.

Growing community of inventors

Hsinchu, Taiwan

Chi-sheng Lin