Powerchip Semiconductor Corporation

Chi-Shan Wu

Cheng-Yuan Hsu

Chih-Wei Hung

Min-San Huang

Chih-Ming Chen

A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.

Manufacturing method a flash memory cell array

Flash memory cell, flash memory cell array and manufacturing method thereof

A manufacturing method of flash memory. A substrate is provided, on which a gate structure is formed. A first spacer is formed on the sidewalls of the gate structure. A source region is formed in the substrate at one side of the gate structure. A first conductive layer and a sacrificial layer are formed on the substrate. The first conductive layer and the sacrificial layer are removed until the gate structure is exposed. A thermal oxidation process is performed to form a mask layer on the first conductive layer and the gate structure. The sacrificial layer remaining on the first conductive layer is removed, and the first conductive layer is etched with a square shape. The mask layer is removed, and a second spacer is formed on the sidewalls of the second conductive layer. A drain region is formed in the substrate at one side of the conductive layer.

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Taipei, Taiwan

Chi-Shan Wu