Conexant Systems, Inc.

Entropic Communications, Inc.

Trident Microsystems (far East) Ltd.

Sony Corporation

Nxp B.v.

Sony Electronics Inc

Maxlinear, Inc.

Chi-ping Nee

Michail Konstantinos Tsatsanis

David Barr

Branislav A Petrovic

Abraham Krieger

Shachar Kons

Chun-Hsuan Kuo

Gadi Kalit

Prasad Shamain

Ali Murat Ficici

Chinh Viet Tran

Donald Brian Eidson

Fred D Harris

Mats Lindstrom

Joseph C Chan

Manjit Singh Gill

Uri Parker

Kendal McNaught-Davis Hess

Yoni Baron

Mike C Wang

Durgaprasad Kashinath Shamain

Gdaliahou Kalit

A method, system and computer program for transmitting at least two payloads in a downstream traffic phase of a time-division duplex (TDD) cycle with a single preamble from a headend followed by concatenated payloads without intervening preambles, whereby the payloads are ranked by increasing modulation profiles. The preamble, and concatenated and ordered set of payloads are then transmitted to two or more predetermined customer premise equipments (CPEs).

Progressive modulation for downstream access

Systems and methods for provided for reducing interference caused by leakage of signals generated by a spread spectrum phase lock loop (SS PLL). Output of SS PLL may be processed to reduce interference. For example, a sinusoidal spreading signal may be used to spread the output of the SS PLL. A notch filter tracks the frequency of the output of the SS PLL to steer the notch in the filter to the instantaneous frequency output from the SS PLL, thus allowing the notch filter to be placed in the path of signals that have unwanted leakage from the SS PLL.

Method and apparatus for cancellation of interference from a spread spectrum phase lock loop

Systems and methods for generating a spurious signal cancellation signal, the system comprising two direct digital synthesizers (DDS). The first DDS provides phase tracking to correct for rounding errors. The second DDS outputs a frequency that is exactly equal to N/M*CLK, where N and M are values selected to set the output frequency equal to the frequency of a spurious signal to be cancelled, and CLK is a clock frequency used to clock the first and second DDS circuits.

Method and system for cancellation of spurious signals

Systems and methods for reducing interference caused by leakage of signals generated by a spread spectrum phase lock loop (SS PLL). The system and method uses a sinusoidal spreading signal to spread the output of a SS PLL. A notch filter tracks the frequency of the output of the SS PLL to steer the notch in the filter to the instantaneous frequency output from the SS PLL, thus allowing the notch filter to be placed in the path of signals that have unwanted leakage from the SS PLL.

Method and apparatus for cancellation of spurious signals

A satellite signal demodulator is configured to use frequency-based channel scanning to sense the presence of a channel and to obtain the frequency profile of the channel. Once the channel is identified and the profile is obtained, channel extraction is used to identify the frequency parameters for a given channel. A coarse parameter estimation is performed to obtain a coarse estimate of the symbol rate (SR) and the center frequency (f) of the channel. The coarse estimation can then be followed by a fine estimation of the symbol rate and center frequency (f), using a bit tracking loop (BTL) lock indicator.

Systems and method for frequency based satellite channel scanning

A modem for use with a computer having a demodulator and a decoder, the modem comprises a hardware interface; a demodulator front-end having a first input and a first output, the first output of the demodulator front-end being configured to interface with the demodulator of the computer and to provide a demodulated front-end signal to the demodulator over the hardware interface; and a forward error correction (FEC) unit having a second input and a second output, the second input of the FEC unit being configured to interface with the demodulator of the computer and to receive a demodulated signal from the demodulator over the hardware interface, the demodulated signal being a demodulation of the demodulated front-end signal, and the second output of the FEC unit being configured to interface with the decoder of the computer and to provide an FEC signal to the decoder over the hardware interface.

System and method for television signal demodulation and decoding

A system for isolating individual channels in a broadcast signal is provided. The system includes a plurality of multipliers, each having an input and an output. A summer coupled to the outputs of each of the plurality of multipliers is provided to generate an output. A multiplication factor system provides a multiplication factor to each of the multipliers to select a predetermined frequency channel of the input signal.

Method and apparatus for channelizing sampled broadband signal

A system for signal processing is provided. The system includes a steady state processing system for receiving a signal. A general purpose processing system is coupled to the steady state processing system and includes a signal acquisition system for receiving the signal and generating acquisition data. The steady state processing system can receive the acquisition data from the signal acquisition system and use the acquisition data to acquire the signal.

Signal acquisition system and method

An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder includes a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Erasures assisted block code decoder and related method

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Chi-ping Nee