Macronix International Co., Ltd.

Chi-Pei Lu

Chun-Lien Su

Shaw-Hung Ku

Guan-De Lee

A method to improve accuracy of a low voltage state in flash memory cells and the memory therewith is proposed. In the method, at least one memory cell is selected from among a plurality of memory cells in the non-volatile memory according to a first voltage and a second voltage. The first voltage is less than the second voltage and greater than or equal to an erase state voltage level of the flash memory, and the second voltage is less than or equal to a read voltage level of the flash memory. A recovery erase operation is applied to the at least one selected memory cell, thereby erasing electrical charges of the at least one selected memory cell to lower a threshold voltage of the at least one selected memory cell.

Method to improve accuracy of a low voltage state in flash memory cells

The present invention provides a manufacturing method of a non-volatile memory including forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first charge blocking layer on the floating gate; forming a nitride layer on the first charge blocking layer; forming a second charge blocking layer on the nitride layer; forming a control gate on the second charge blocking layer; and performing a treatment to the nitride layer to get a higher dielectric constant.

Manufacturing method of non-volatile memory

A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a gate dielectric layer, a floating gate, a control gate, an inter-gate dielectric structure and two doped regions. The gate dielectric layer is disposed on a substrate. The floating gate is disposed on the gate dielectric layer. The control gate is disposed on the floating gate. The inter-gate dielectric structure is disposed between the control gate and the floating gate. The inter-gate dielectric structure includes a first oxide layer, a second oxide layer and a charged nitride layer. The first oxide layer is disposed on the floating gate. The second oxide layer is disposed on the first oxide layer. The charged nitride layer is disposed between the first oxide layer and the second oxide layer. The doped regions are disposed in the substrate at two sides of the floating gate, respectively.

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Hsinchu, Taiwan

Chi-Pei Lu