Taiwan Semiconductor Manufacturing Comp. Ltd.

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Taiwan Semiconductir Manufacturing Co., Ltd.

Chi On Chui

Sai-Hooi Yeong

Hsin-Yi Lee

Bo-Feng Young

Cheng-Lung Hung

Yung-Cheng Lu

Che-Hao Chang

Chung-Ting Ko

Te-Yang Lai

Weng Chang

Chun-Yen Peng

Yu-Ming Lin

Tai-Chun Huang

Chih-Yu Chang

Bo-Cyuan Lu

Chun-Heng Chen

Wan-Yi Kao

Chunyao Wang

Kai-Hsuan Lee

Ziwei Fang

Huang-Lin Chao

Chung-Chiang Wu

Xiong-Fei Yu

Chenchen Jacob Wang

Ting-Gang Chen

Ji-Cheng Chen

Meng-Han Lin

Cheng-Ming Lin

Jr-Hung Li

Wen-Kai Lin

Shu-Han Chen

Yen-Ming Chen

Yee-Chia Yeo

Sung-Li Wang

Jyh-Cherng Sheu

Cheng-Hao Hou

Sheng-Chen Wang

Han-Jong Chia

Hsien-Ming Lee

Chia-Ta Yu

Chia-Wei Hsu

Sung-En Lin

Tze-Liang Lee

Da-Yuan Lee

Chien-Hao Chen

Bo-Yu Lai

Kun-Yu Lee

Kuei-Lun Lin

Chih-Wei Chang

Chun-Chieh Lu

Chih-Tang Peng

Jian-Hao Chen

Huang-Yi Huang

Shih-Hang Chiu

Wei-Chin Lee

Chih-Hao Wang

Feng-Cheng Yang

Hung-Li Chiang

I-Sheng Chen

Chia-Ching Lee

Wei-Cheng Wang

Hung-Chin Chung

Kuan-Ting Liu

Syun-Ming Jang Jang

Pei-Yu Wang

Cheng-Yu Yang

Sen-Hong Syue

Chia-Wei Chen

Chien Ning Yao

Kuo-Cheng Ching

Mei-Yun Wang

Ming-Ching Chang

Ryan Chia-Jen Chen

Fu-Kai Yang

Chen-Ming Lee

Ying-Keung Leung

Shu-Yuan Ku

I-Wen Wu

Ming-Jie Huang

Chun-Han Chen

Chia-Yuan Chang

Wei-Yang Lee

Chung-Liang Cheng

Szu-Ying Chen

Kuo-Feng Yu

Shih-Hao Lin

Mao-Lin Huang

Ku-Feng Yang

Lung-Kun Chu

Cheng-Tung Lin

Yuan-Ching Peng

Min Cao

Jiun-Ming Kuo

Tzer-Min Shen

Hui-Chi Chen

Zhen-Cheng Wu

Hsiang-Pi Chang

Min-Hsiu Hung

Yen-Chun Huang

Chih-Chung Chang

A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.

Metal gate structure and method of forming the same

A semiconductor device includes nanosheets between the source/drain regions, and a gate structure over the substrate and between the source/drain regions, the gate structure including a gate dielectric material around each of the nanosheets, a work function material around the gate dielectric material, a first capping material around the work function material, a second capping material around the first capping material, wherein the second capping material is thicker at a first location between the nanosheets than at a second location along a sidewall of the nanosheets, and a gate fill material over the second capping material.

Gates structures of nanostructure field-effect transistors (nano-FETs) including a plurality of semiconductor based capping materials and methods of forming the same

A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl)CH), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

Reducing k values of dielectric films through anneal

In an embodiment, a device includes: a first nanostructure; a gate dielectric layer around the first nanostructure; a first p-type work function tuning layer on the gate dielectric layer; a dielectric barrier layer on the first p-type work function tuning layer; and a second p-type work function tuning layer on the dielectric barrier layer, the dielectric barrier layer being thinner than the first p-type work function tuning layer and the second p-type work function tuning layer.

Transistor gate structures and methods of forming the same

In an embodiment, a semiconductor device is provided, which includes a first doped gate dielectric layer and a second doped gate dielectric layer, wherein the first doped gate dielectric layer and the second doped gate dielectric layer comprise a high-k material doped with a dipole dopant. The second doped gate dielectric layer has a second concentration of the first dipole dopant. The concentration of the dipole dopant in the first doped gate dielectric layer is greater than the concentration, and the concentration peak of the dipole dopant in the first doped gate dielectric layer is deeper than the concentration peak of the dipole dopant in the second doped gate dielectric layer. A first gate electrode over the first doped gate dielectric layer, and a second gate electrode over the second doped gate dielectric layer, the first gate electrode and the second gate electrode have a same width.

Semiconductor device having doped gate dielectric layer and method for forming the same

A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nanostructure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.

Transistor gate structure and method of forming

A semiconductor structure includes gate spacers disposed over a semiconductor layer, a hafnium-containing dielectric layer, where a first portion of the hafnium-containing dielectric layer having a first thickness is disposed over the semiconductor layer and a second portion of the hafnium-containing dielectric layer having a second thickness is disposed along sidewalls of the gate spacers, and where the first thickness is greater than the second thickness, and a metal gate electrode disposed over the hafnium-containing dielectric layer and between the gate spacers.

Fabrication of field effect transistors with ferroelectric materials

The present disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes a first nanosheet channel structure and a first high-k dielectric layer surrounding the first nanosheet channel structure. In addition, the semiconductor structure includes a second nanosheet channel structure disposed above and substantially parallel to the first nanosheet channel structure, and a second high-k dielectric layer surrounding the second nanosheet channel structure. The semiconductor structure further includes a work function adjustment layer including silicon and disposed between the first high-k dielectric layer and the second high-k dielectric layer. The first high-k dielectric layer and the second high-k dielectric layer are separated by the work function adjustment layer.

Semiconductor structure including nanosheet channel structure and method for forming the same

A semiconductor device includes a first device over a substrate, wherein the first device includes a gate stack including a gate electrode material; a source/drain region in the substrate adjacent the gate stack; a first isolation region surrounding the gate stack; a gate contact over and contacting the gate stack, wherein the gate contact includes a gate contact material; and a second isolation region surrounding the gate contact; and a second device over the substrate, wherein the second device includes a first parallel capacitor including first electrodes, wherein the first electrodes include the gate electrode material, wherein the first isolation region separates the first electrodes; and a second parallel capacitor over the first parallel capacitor, wherein the second parallel capacitor includes second electrodes connected to the first electrodes, wherein the second electrodes include the gate contact material, wherein adjacent second electrodes are separated by the second isolation region.

Semiconductor device and method for forming capacitor structure

An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.

Semiconductor device and method

Semiconductor devices and methods of manufacturing are presented wherein a gate dielectric is treated within an analog region of a semiconductor substrate. The gate dielectric may be treated with a plasma exposure and/or an annealing process in order to form a recovered region of the gate dielectric. A separate gate dielectric is formed within a logic region of the semiconductor substrate, and a first gate electrode and second gate electrode are formed over the gate dielectrics.

Semiconductor device and method of manufacturing

The present disclosure describes a method for forming a semiconductor device having a work function metal layer doped with tantalum to mitigate oxygen diffusion and improve device threshold voltage. The method includes forming a gate dielectric layer on a channel structure and forming a work function metal layer on the gate dielectric layer. The gate dielectric layer includes an interfacial layer on the channel structure and a high-k dielectric layer on the interfacial layer. The method further includes doping the work function metal layer and the gate dielectric layer with tantalum.

Work function tuning in semiconductor devices

A method includes forming an oxide layer on a semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and contacting a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, performing an annealing process to drive-in a dipole dopant in the dipole film into the layer, removing the dipole film, and forming a gate electrode over the second high-k dielectric layer.

Dipole-engineered high-k gate dielectric and method forming same

Methods for selectively depositing a metal layer over a gate structure and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate structure over the channel region; a gate spacer adjacent the gate structure; a first dielectric layer adjacent the gate spacer; a barrier layer contacting a top surface of the gate spacer and a side surface of the first dielectric layer, the barrier layer including a nitride; and a metal layer over the gate structure adjacent the barrier layer, the metal layer having a first width equal to a second width of the gate structure.

The present disclosure provides a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer, at least a portion of the ferroelectric layer is between the metal gate layer and the substrate, wherein the ferroelectric layer includes hafnium oxide-based material, the hafnium oxide-based material includes a first portion of hafnium oxide with orthorhombic phase, a second portion of hafnium oxide with monoclinic phase, and a third portion of the hafnium oxide with tetragonal phase, wherein a first volume of the first portion is greater than a second volume of the second portion, and the second volume of the second portion is greater than a third volume the third portion.

Semiconductor structure and manufacturing method for the semiconductor structure

Growing community of inventors

Hsinchu, Taiwan

Chi On Chui