Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Chi On Chui

Sai-Hooi Yeong

Hsin-Yi Lee

Bo-Feng Young

Cheng-Lung Hung

Yung-Cheng Lu

Weng Chang

Che-Hao Chang

Chung-Ting Ko

Te-Yang Lai

Yu-Ming Lin

Chun-Yen Peng

Tai-Chun Huang

Chih-Yu Chang

Bo-Cyuan Lu

Chun-Heng Chen

Huang-Lin Chao

Wan-Yi Kao

Chunyao Wang

Kai-Hsuan Lee

Xiong-Fei Yu

Ji-Cheng Chen

Meng-Han Lin

Ziwei Fang

Chung-Chiang Wu

Cheng-Ming Lin

Chenchen Jacob Wang

Ting-Gang Chen

Wen-Kai Lin

Shu-Han Chen

Jr-Hung Li

Yee-Chia Yeo

Yen-Ming Chen

Sung-Li Wang

Jyh-Cherng Sheu

Cheng-Hao Hou

Han-Jong Chia

Sheng-Chen Wang

Chien-Hao Chen

Hsien-Ming Lee

Chia-Ta Yu

Chia-Wei Hsu

Sung-En Lin

Tze-Liang Lee

Da-Yuan Lee

Bo-Yu Lai

Hung-Li Chiang

Chih-Wei Chang

I-Sheng Chen

Chun-Chieh Lu

Chih-Tang Peng

Jian-Hao Chen

Huang-Yi Huang

Shih-Hang Chiu

Wei-Chin Lee

Chih-Hao Wang

Feng-Cheng Yang

Chia-Ching Lee

Wei-Cheng Wang

Hung-Chin Chung

Kuan-Ting Liu

Chia-Wei Chen

Syun-Ming Jang Jang

Pei-Yu Wang

Cheng-Yu Yang

Sen-Hong Syue

Chien Ning Yao

Kuo-Cheng Ching

Mei-Yun Wang

Fu-Kai Yang

Ming-Ching Chang

Ryan Chia-Jen Chen

Szu-Ying Chen

Chen-Ming Lee

Mao-Lin Huang

Ying-Keung Leung

Shu-Yuan Ku

Lung-Kun Chu

I-Wen Wu

Hui-Chi Chen

Zhen-Cheng Wu

Ming-Jie Huang

Chun-Han Chen

Po-Hsien Cheng

Wei-Yang Lee

Chung-Liang Cheng

Kuo-Feng Yu

Shih-Hao Lin

Ku-Feng Yang

Cheng-Tung Lin

Yuan-Ching Peng

Min Cao

Tzer-Min Shen

Jiun-Ming Kuo

Chih-Wei Lee

Hsiang-Pi Chang

Min-Hsiu Hung

Yen-Chun Huang

Yi-Ting Wang

Chih-Chung Chang

A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure includes a fin and a layer stack over the fin, the layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure over the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting an upper layer of the fin exposed at a bottom of the opening into a seed layer by performing an implantation process; selectively depositing a dielectric layer over the seed layer at the bottom of the opening; and selectively growing a source/drain material on opposing sidewalls of the second semiconductor material exposed by the opening.

Nanostructure field-effect transistor device and method of forming

A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Semiconductor device having multi-layer epitaxial structures with different lattice constants

A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer forming a gate stack.

NFET with aluminum-free work-function layer and method forming same

A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes removing the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor lavers. The method further includes forming a gate dielectric layer to wrap around the semiconductor nanostructures and forming a first metal-containing layer over the gate dielectric layer to wrap around the semiconductor nanostructures. In addition, the method includes introducing oxygen-containing plasma on the first metal-containing layer to transform an upper portion of the first metal-containing layer into a metal oxide layer. The method includes forming a second metal-containing layer over the metal oxide layer.

Formation of a semiconductor device with a gate containing a metal oxide layer using an oxidation process

In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a n-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a p-type work function metal, the p-type work function metal different from the n-type work function metal; and a fill layer on the second work function tuning layer.

Semiconductor device and method

A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

Replacement gate methods that include treating spacers to widen gate

A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive.

Fluorine incorporation method for nanosheet

A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, with the semiconductor region being exposed to the trench, forming a gate dielectric layer extending into the trench, and depositing a work-function tuning layer on the gate dielectric layer. The work-function tuning layer comprises aluminum and carbon. The method further includes depositing a p-type work-function layer over the work-function tuning layer, and performing a planarization process to remove excess portions of the p-type work-function layer, the work-function tuning layer, and the gate dielectric layer to form a gate stack.

Work-function layers in the gates of pFETs

An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.

Memory cell and method

Semiconductor devices and methods of manufacturing the semiconductor devices are disclosed herein. The methods include forming nanostructures in a multilayer stack of semiconductor materials. An interlayer dielectric is formed surrounding the nanostructures and a gate dielectric is formed surrounding the interlayer dielectric. A first work function layer is formed over the gate dielectric. Once the first work function layer has been formed, an annealing process is performed on the resulting structure and oxygen is diffused from the gate dielectric into the interlayer dielectric. After performing the annealing process, a second work function layer is formed adjacent the first work function layer. A gate electrode stack of a nano-FET device is formed over the nanostructures by depositing a conductive fill material over the second work function layer.

Semiconductor device and methods of manufacture

A device includes a semiconductor substrate; a vertically stacked set of nanostructures over the semiconductor substrate; a first source/drain region; and a second source/drain region, wherein the vertically stacked set of nanostructures extends between the first source/drain region and the second source/drain region along a first cross-section. The device further includes a gate structure encasing the vertically stacked set of nanostructures along a second cross-section. The second cross-section is along a longitudinal axis of the gate structure. The gate structure comprises: a gate dielectric encasing each of the vertically stacked set of nanostructures; a first metal carbide layer over the gate dielectric; and a gate fill material over the first metal carbide layer. The first metal carbide layer comprises Ce, Hf, V, Nb, Sc, Y, or Mo.

Transistor gate structures and methods of forming thereof

A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.

Metal gate structure and method of forming the same

A semiconductor device includes nanosheets between the source/drain regions, and a gate structure over the substrate and between the source/drain regions, the gate structure including a gate dielectric material around each of the nanosheets, a work function material around the gate dielectric material, a first capping material around the work function material, a second capping material around the first capping material, wherein the second capping material is thicker at a first location between the nanosheets than at a second location along a sidewall of the nanosheets, and a gate fill material over the second capping material.

Gates structures of nanostructure field-effect transistors (nano-FETs) including a plurality of semiconductor based capping materials and methods of forming the same

A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl)CH), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

Reducing k values of dielectric films through anneal

In an embodiment, a device includes: a first nanostructure; a gate dielectric layer around the first nanostructure; a first p-type work function tuning layer on the gate dielectric layer; a dielectric barrier layer on the first p-type work function tuning layer; and a second p-type work function tuning layer on the dielectric barrier layer, the dielectric barrier layer being thinner than the first p-type work function tuning layer and the second p-type work function tuning layer.

Transistor gate structures and methods of forming the same

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Hsinchu, Taiwan

Chi On Chui