Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Chi On Chui

Sai-Hooi Yeong

Hsin-Yi Lee

Cheng-Lung Hung

Bo-Feng Young

Yung-Cheng Lu

Weng Chang

Che-Hao Chang

Te-Yang Lai

Chung-Ting Ko

Yu-Ming Lin

Tai-Chun Huang

Chun-Yen Peng

Chih-Yu Chang

Bo-Cyuan Lu

Wan-Yi Kao

Chun-Heng Chen

Huang-Lin Chao

Chunyao Wang

Kai-Hsuan Lee

Xiong-Fei Yu

Ji-Cheng Chen

Meng-Han Lin

Ziwei Fang

Chung-Chiang Wu

Cheng-Ming Lin

Chenchen Jacob Wang

Ting-Gang Chen

Shu-Han Chen

Wen-Kai Lin

Jr-Hung Li

Yee-Chia Yeo

Yen-Ming Chen

Sung-Li Wang

Jyh-Cherng Sheu

Cheng-Hao Hou

Han-Jong Chia

Sheng-Chen Wang

Tze-Liang Lee

Da-Yuan Lee

Chien-Hao Chen

Hsien-Ming Lee

Chia-Ta Yu

Chia-Wei Hsu

Sung-En Lin

Bo-Yu Lai

Shih-Hang Chiu

Hung-Li Chiang

Chih-Wei Chang

I-Sheng Chen

Chun-Chieh Lu

Chih-Tang Peng

Jian-Hao Chen

Huang-Yi Huang

Wei-Cheng Wang

Kuan-Ting Liu

Chia-Wei Chen

Wei-Chin Lee

Chih-Hao Wang

Feng-Cheng Yang

Chia-Ching Lee

Hung-Chin Chung

Syun-Ming Jang Jang

Pei-Yu Wang

Zhen-Cheng Wu

Sen-Hong Syue

Cheng-Yu Yang

Chien Ning Yao

Po-Hsien Cheng

Kuo-Cheng Ching

Mei-Yun Wang

Fu-Kai Yang

Ming-Ching Chang

Ryan Chia-Jen Chen

Szu-Ying Chen

Chen-Ming Lee

Mao-Lin Huang

Ying-Keung Leung

Shu-Yuan Ku

Lung-Kun Chu

I-Wen Wu

Hui-Chi Chen

Chih-Wei Lee

Ming-Jie Huang

Chun-Han Chen

Wei-Yang Lee

Chung-Liang Cheng

Shih-Hao Lin

Kuo-Feng Yu

Ku-Feng Yang

Cheng-Tung Lin

Yuan-Ching Peng

Min Cao

Tzer-Min Shen

Jiun-Ming Kuo

Hsiang-Pi Chang

Min-Hsiu Hung

Yen-Chun Huang

Yi-Ting Wang

Chih-Chung Chang

A method includes forming a first dummy gate stack on a protruding semiconductor fin, etching the first dummy gate stack to form a trench, extending the trench downwardly to penetrate through a portion of the protruding semiconductor fin, and filling the trench with a dielectric material to form a fin isolation region. A seam is formed in the fin isolation region, and the seam extends to a level lower than a top surface level of the protruding semiconductor fin. The seam has a top width smaller than about 1 nm. A second dummy gate stack on the protruding semiconductor fin is replaced with a replacement gate stack.

Forming seams with desirable dimensions in isolation regions

A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.

Semiconductor device and method of forming the same

Methods of forming vias for coupling source/drain regions to backside interconnect structures in semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a conductive feature adjacent a gate structure; a dielectric layer on the conductive feature and the gate structure; a metal via embedded in the dielectric layer; and a liner layer between and in contact with the metal via and the dielectric layer, the liner layer being boron nitride.

Semiconductor devices including backside power via and methods of forming the same

In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a p-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a n-type work function metal, the n-type work function metal different from the p-type work function metal; and a fill layer on the second work function tuning layer.

Transistor gate structures and methods of forming the same

In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, an isolation insulating layer is formed such that an upper portion of the fin structure protrudes from the isolation insulating layer, a gate dielectric layer is formed by a deposition process, a nitridation operation is performed on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The gate dielectric layer as formed includes silicon oxide, and the nitridation operation comprises a plasma nitridation operation using a Ngas and a NHgas.

Method of manufacturing semiconductor devices and semiconductor devices

In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.

Methods of forming semiconductor devices

A method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin that protrudes above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin that protrudes above the substrate, where the first and the second nanostructures include a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first and the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process.

Nanostructure field-effect transistor device and method of forming

A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, where the first semiconductor fin and the second semiconductor fin extend upwards from a semiconductor substrate, depositing a second dielectric layer over the first dielectric layer, depositing a third dielectric layer over the second dielectric layer, where materials of the second dielectric layer and the third dielectric layer are different, and a material of the first dielectric layer is different from the material of the second dielectric layer and recessing the first dielectric layer and the second dielectric layer to expose sidewalls of the first semiconductor fin and the second semiconductor fin and to form a dummy fin between the first semiconductor fin and the second semiconductor fin.

Dummy Fin structures and methods of forming same

A method according to the present disclosure includes providing a substrate that includes a dummy gate stack wrapping over an active region, and a spacer layer extending along sidewalls of the dummy gate stack, selectively removing the dummy gate stack to form a gate trench exposing the active region, depositing a gate dielectric over the active region, depositing at least one work function layer over the gate dielectric layer, depositing a tungsten layer over the at least one work function layer, and depositing a tungsten nitride layer over the tungsten layer.

Gate structures for multi-gate devices

Embodiments include a device and method of forming a device, such as a nano-FET transistor, including a first nanostructure. A gate dielectric is formed around the first nanostructure. A gate electrode is formed over the gate dielectric, and the gate electrode includes a first work function metal. In the gate electrode, a first metal residue is formed at an interface between the gate dielectric and the first work function metal as a result of a treatment process performed prior to forming the first work function metal. The first metal residue has a metal element that is different than a metal element of the first work function metal.

Gate structures in transistors and method of forming same

Ruthenium of a metal gate (MG) and/or a middle end of line (MEOL) structure is annealed to reduce, or even eliminate, seams after the ruthenium is deposited. Because the annealing reduces (or removes) seams in deposited ruthenium, electrical performance is increased because resistivity of the MG and/or the MEOL structure is decreased. Additionally, for MGs, the annealing generates a more even deposition profile, which results in a timed etching process producing a uniform gate height. As a result, more of the MGs will be functional after etching, which increases yield during production of the electronic device.

Techniques for semiconductor gate and contact formation to reduce seam formation

A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure includes a fin and a layer stack over the fin, the layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure over the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting an upper layer of the fin exposed at a bottom of the opening into a seed layer by performing an implantation process; selectively depositing a dielectric layer over the seed layer at the bottom of the opening; and selectively growing a source/drain material on opposing sidewalls of the second semiconductor material exposed by the opening.

A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Semiconductor device having multi-layer epitaxial structures with different lattice constants

A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer forming a gate stack.

NFET with aluminum-free work-function layer and method forming same

A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes removing the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor lavers. The method further includes forming a gate dielectric layer to wrap around the semiconductor nanostructures and forming a first metal-containing layer over the gate dielectric layer to wrap around the semiconductor nanostructures. In addition, the method includes introducing oxygen-containing plasma on the first metal-containing layer to transform an upper portion of the first metal-containing layer into a metal oxide layer. The method includes forming a second metal-containing layer over the metal oxide layer.

Formation of a semiconductor device with a gate containing a metal oxide layer using an oxidation process

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Hsinchu, Taiwan

Chi On Chui