Freescale Semiconductor,inc.

Motorola Corporation

Chi Nan Brian Li

Cheong Min Hong

Alexander Hoefler

Rana P Singh

Gowrishankar L Chindalore

Ko-Min Chang

Kuo-Tung Chang

Der-Gao Lin

Floating gates are formed in two separate polysilicon depositions steps resulting in distinct portions. The first formed portions are between isolation regions. A thick insulator is formed over the isolation regions and floating gate portions. The thick insulator is patterned to leave fences over the isolation regions. A thinning process, an isotropic etch in this example, is applied to these fences to make them thinner. Polysilicon sidewall spacers are formed on the sides of these fences. These sidewall spacers become the second portion of the floating gate. These second portions have the desired shape for significantly increasing the capacitance to the subsequently formed control gates, thereby reducing the gate voltage required for programming and erasing made by a relatively robust process.

Method for making a semiconductor device with reduced spacing

A method for forming a semiconductor device includes providing a semiconductor substrate comprising silicon, forming a layer of dielectric on the surface of the semiconductor substrate, forming a gate electrode comprising silicon over the layer of dielectric, recessing the layer of dielectric under the gate electrode, filling the recess with a discrete charge storage material, oxidizing a portion of the gate electrode, and oxidizing a portion of the semiconductor substrate.

Method of forming a semiconductor device and structure thereof

A memory and a method for programming a memory device are discussed. The method comprises selecting a cell to program, wherein the cell is coupled to a bit line, applying a first programming pulse, wherein the first programming pulse comprises applying a first voltage to the bit line, verifying if the cell is programmed after applying the first programming pulse, and applying a second programming pulse to the bit line after applying the first programming pulse if the cell is not programmed after applying the first programming pulse, wherein second programming pulse comprises applying a second voltage to the bit line, wherein the second voltage is different than the first voltage.

Memory structure and method of programming

In some embodiments, non-volatile memory (NVM) devices are formed on a silicon-on-insulator (SOI) substrate () by forming elevated sources and drains () in contact with extensions () within the top silicon layer () of the SOI substrate (). Buried conductive regions () are formed within the top silicon layer () below the extensions () to mitigate floating body effects that occur when using SOI substrates. In other embodiments, NVM devices are formed using elevated sources and drains (), extensions () and the buried conductive regions () in bulk semiconductor substrates. In any embodiment, logic devices may be formed in conjunction with NVM devices, wherein the logic and NVM devices have elevated sources and drains (), extensions () and the buried conductive regions ().

Method of forming a semiconductor device in a semiconductor layer and structure thereof

An active fuse includes an active fuse geometry () that is used to form both a variable resistor () and a select transistor (). In one embodiment, the active fuse geometry is formed in a portion of an active region () of a semiconductor substrate (), and a select gate () is disposed over an end portion () of the active fuse geometry to form an integral select transistor () for use in programming the active fuse. The use of a shared active fuse geometry within the active region allows for reduced area requirements and improved sensing margins.

Fuse and method for forming

A method of erasing a semiconductor nonvolatile memory (NVM) so as to compact the distribution of cell erased threshold voltages within a restricted range around a target erased threshold voltage. Erase pulses are applied to NVM cells until a determination is made by, for example, sensing total column source current that adequate erasure has been realized. An optional soft program signal may be applied subsequent to each erase pulse in order to impede over-erasure. Once erasure has been verified, the distribution of erased threshold voltages is compacted by sustaining, for a predetermined length of time, the simultaneous application of a gate voltage that is equal to the target erased threshold voltage and a highly positive drain voltage.

Compaction scheme in NVM

A first plurality of memory cells ( ) connected in series lies within a first well ( ) that is separated and electrically isolated ( ) from a second plurality of memory cells ( et al.) connected in series lying within a second well ( ). In one embodiment, the first and second wells ( ) are doped p-type and are contained within an n-well ( ) and a substrate ( ). Applying a negative voltage to its corresponding bit line and a positive voltage to its corresponding word line programs a predetermined memory cell within the first plurality. A lesser positive voltage than that applied to the predetermined memory cell's word line is applied to all other bit lines and word lines of non-selected memory cells. By utilizing a negative voltage while programming a memory cell, the magnitude of programming voltages is reduced, thereby, removing the need for an elaborate charge pump to generate a much higher programming voltage.

Non-volatile memory with a serial transistor structure with isolated well and method of operation

Semiconductor devices and processes for forming the same. The semiconductor device includes field isolation regions within trenches lying within a semiconductor device substrate. The trenches include a first trench and a second trench. The device includes a first component region and a second component region. The first component region lies near the first trench, and the second component region lies near the second trench. The semiconductor device includes a feature selected from a group consisting of: (a) a first liner within the first trench, and a second liner within the second trench, wherein the first liner is significantly thicker than the second liner; and (b) the first component region has a first edge with a first radius of curvature near the first trench, and the second component has a second edge with a second radius of curvature near the second trench, wherein the first radius of curvature is significantly greater than the second radius of curvature.

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Austin, TX, United States of America

Chi Nan Brian Li