Xilinx, Inc.

Lattice Semiconductor Corporation

Chi Minh Nguyen

Robert I Fu

Brian C Gaide

Satwant Singh

Ting Yew

Ann Wu

Martin L Voogel

James M Simkins

Ilya K Ganusov

Chan-Chi Jason Cheng

Timothy Scott Swensen

Brian D Philoksky

Giai Trinh

Yi Chiang

The disclosed circuit arrangements include a logic circuit, input register logic coupled to the logic circuit and including a first plurality of bi-stable circuits and a control circuit coupled to the input register logic. The control circuit is configured to generate a plurality of delayed clock signals from an input clock signal. The plurality of delayed clock signals include a first delayed clock signal and a second delayed clock signal. The control circuit selectively provides one or more of the delayed clock signals or the input clock signal to clock inputs of the first plurality of bi-stable circuits and selectively provides one or more of the delayed clock signals or the input clock signal to the logic circuit. The control circuit includes a variable clock delay logic circuit configured to equalize a clock delay to the input register logic with a clock delay to the logic circuit.

Selectively providing clock signals using a programmable control circuit

The disclosed voting circuit includes a pull-up circuit connected to an output node and to a positive supply voltage. A pull-down circuit is connected to the output node and to ground, and the output node is coupled to receive true output of a first bi-stable circuit. The pull-up circuit pulls the output node to the positive supply voltage in response to complementary output signals from second and third bi-stable circuits being in a first state, and the pull-down circuit pulls the output node to ground in response to complementary output signals from second and third bi-stable circuits being in a second state that is opposite the first state.

Voting circuit and self-correcting latches

Integrated circuits having groups of flip-flops with the option to ignore control signals are disclosed. For example, an integrated circuit comprises a first group and a second group of flip-flops that share a common reset signal, and a first selection unit for selecting a first output from among the common reset signal and a logical low signal to be sent to the second group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the second group. The integrated circuit may also include a second selection unit for selecting a second output from among the common reset signal and a logical low signal to be sent to the first group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the first group.

Flip-flop array with option to ignore control signals

A method of preventing an unintentional state change in a data storage node of a latch is disclosed. The method comprises receiving a reference input signal; generating a delayed input signal based upon the reference clock signal; maintaining a state of a first data storage node of a plurality of data storage nodes by latching data at the first node using the reference input signal; and maintaining a state of a second data storage node of the plurality of data storage nodes by latching data at the second data storage node using the delayed input signal. A circuit for preventing an unintentional state change in a data storage node of a latch is also disclosed.

Structures and methods of preventing an unintentional state change in a data storage node of a latch

A programmable logic device, in accordance with an embodiment of the present invention, includes a plurality of multiplexers, having fuse input terminals and input signal terminals, and a plurality of associated fuses providing fuse signals to the fuse input terminals to control selection of the input signal terminals. The fuses in a first state select a first input signal terminal of the input signal terminals, with a first multiplexer from the plurality of multiplexers receiving a first logic level signal at the first input signal terminal and providing the first logic level signal to the first input signal terminal of a first set of the plurality of multiplexers. The fuses associated with the first set are adapted to be programmed before the fuses associated with the first multiplexer.

Multiplexer initialization systems and methods

In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.

Growing community of inventors

San Jose, CA, United States of America

Chi Minh Nguyen