Growing community of inventors

Cupertino, CA, United States of America

Chi-Ming Yeung

Average Co-Inventor Count = 3.88

ph-index = 4

The patent ph-index is calculated by counting the number of publications for which an author has been cited by other authors at least that same number of times.

Forward Citations = 30

Chi-Ming YeungYoshie Nakabayashi (10 patents)Chi-Ming YeungThomas J Giovannini (9 patents)Chi-Ming YeungHenry Stracovsky (9 patents)Chi-Ming YeungRichard E Perego (3 patents)Chi-Ming YeungSteven Cameron Woo (3 patents)Chi-Ming YeungLawrence Lai (3 patents)Chi-Ming YeungDavid A Secker (3 patents)Chi-Ming YeungPradeep Batra (3 patents)Chi-Ming YeungVlad Fruchter (2 patents)Chi-Ming YeungFrederick Abbott Ware (1 patent)Chi-Ming YeungKyung Suk Oh (1 patent)Chi-Ming YeungKeith Lowery (1 patent)Chi-Ming YeungRavindranath T Kollipara (1 patent)Chi-Ming YeungDonald R Mullen (1 patent)Chi-Ming YeungShajith Musaliar Sirajudeen (1 patent)Chi-Ming YeungChi-Ming Yeung (17 patents)Yoshie NakabayashiYoshie Nakabayashi (10 patents)Thomas J GiovanniniThomas J Giovannini (64 patents)Henry StracovskyHenry Stracovsky (11 patents)Richard E PeregoRichard E Perego (145 patents)Steven Cameron WooSteven Cameron Woo (92 patents)Lawrence LaiLawrence Lai (58 patents)David A SeckerDavid A Secker (38 patents)Pradeep BatraPradeep Batra (21 patents)Vlad FruchterVlad Fruchter (24 patents)Frederick Abbott WareFrederick Abbott Ware (776 patents)Kyung Suk OhKyung Suk Oh (82 patents)Keith LoweryKeith Lowery (27 patents)Ravindranath T KolliparaRavindranath T Kollipara (26 patents)Donald R MullenDonald R Mullen (11 patents)Shajith Musaliar SirajudeenShajith Musaliar Sirajudeen (5 patents)
..
Inventor’s number of patents
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Strength of working relationships

Company Filing History:

1. Rambus Inc. (17 from 2,861 patents)


17 patents:

1. 12141081 - Training and operations with a double buffered memory topology

2. 11907139 - Memory system design using buffer(s) on a mother board

3. 11768780 - Training and operations with a double buffered memory topology

4. 11537540 - Memory system design using buffer(s) on a mother board

5. 11294830 - Training and operations with a double buffered memory topology

6. 11003601 - Memory system design using buffer(s) on a mother board

7. 10614002 - Memory system design using buffer(S) on a mother board

8. 10613995 - Training and operations with a double buffered memory topology

9. 10255220 - Dynamic termination scheme for memory communication

10. 10169258 - Memory system design using buffer(s) on a mother board

11. 9921751 - Methods and systems for mapping a peripheral function onto a legacy memory interface

12. 9880971 - Memory appliance for accessing memory

13. 9841791 - Circuit board assembly configuration

14. 9824779 - Memory error repair

15. 9275733 - Methods and systems for mapping a peripheral function onto a legacy memory interface

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