Sandisk Corporation

Sandisk Technologies Inc.

Catalyst Semiconductor, Inc.

Chi-Ming Wang

Daniel C Guterman

George Samachisa

Brian Murphy

Khandker N Quader

Jian Feng Chen

Raul-Adrian Cernea

Man Lung Mui

Douglas J Lee

Rushyah Tang

Seungpil Lee

Hao Nguyen

John S Mangan

Yan Li

Johann Alsmeier

Henry Chien

Raul Adrian Cernea

Xiying Costa

Bo Liu

Kwang-Ho Kim

Alexander Kwok-Tung Mak

Eugene Jinglun Tam

Fanglin Zhang

Shouchang Tsao

Kuo-Lung Chen

Christopher John Petti

Feng Q Pan

Kevin M Conley

Yung-Tin Chen

Geoffrey Steven Gongwer

Yongliang Wang

Trung Pham

Prashanti Govindu

Cuong Quoc Trinh

Akira Takahashi

Yong Wang

Hiten D Randhawa

Anil Gupta

Jian Chen

Gyuwan Kwon

Hao Thai Nguyen

A vertical NAND string device includes a semiconductor channel, where at least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of a substrate, at least one semiconductor or electrically conductive landing pad embedded in the semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate.

Vertical NAND and method of making thereof using sequential stack etching and landing pad

Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and 'folded' within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is 'unfolded' is also described. A register structure allowing such a &#x201c;folding&#x201d; operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

Structure and method for shuffling data within non-volatile memory devices

Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.

High speed sense amplifier array and method for non-volatile memory

Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and 'folded' within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is 'unfolded' is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a &#x201c;folding&#x201d; operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result of the sensing to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, by which current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination of the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of this determination; and a transfer gate coupled to the data latch to supply a latched result to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.

Nonvolatile memory with a current sense amplifier having a precharge circuit and a transfer gate coupled to a sense node

A pull down circuit pulls a bit line voltage to a regulated source voltage in a non-volatile storage device during a sense operation such as a verify operation which occurs during programming. The storage device may include NAND strings which have associated bit lines and sense components, and a common source line. When a selected storage element of a NAND string has been programmed to its intended state, the bit line is locked out during subsequent verify operations which occur for other NAND strings which are not yet locked out. The pull down device is coupled to each bit line and to the common source line, whose voltage is regulated at a positive DC level, to prevent coupling of system power bus (V) noise from the locked out bit lines to the not yet locked out bit lines.

Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise

Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations. A second program voltage step size that is larger than a nominal step size is used in one embodiment when programming select memory cells or word lines, such as the last word line to be programmed for a NAND string.

Variable reading of non-volatile memory

Systems for variable reading in non-volatile memory

In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

Method of reducing disturbs in non-volatile memory

According to different embodiments of the present invention, various methods, devices and systems are described for managing power in charge pumps in a non-volatile memory system having a high voltage charge pump and associated regulator. A method includes the following operations, receiving an operation command corresponding to an operation, pumping up a charge pump output voltage to a desired output voltage, turning off the regulator and the charge pump when the output voltage is approximately the desired output voltage compensating for charge sharing by turning on the charge pump and setting a pump clock rate to a slow clock rate in order to avoid overshooting the desired output voltage by the charge pump while the operation is being carried out, and compensating for junction leakage by turning on the regulator and the charge pump until the charge pump output voltage is the desired output voltage.

Implementation of output floating scheme for hv charge pumps

A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches connected together in parallel between two power supply lines. A current mirroring scheme limits current supplied to the latch. This reduces a difference of the two supplies, positive voltage, ground, or negative voltages, during data changes. The circuit provides smaller device sizes and fast speeds when data changes in the latch, while also providing lower power consumption. The technique provides greater benefits as the voltage difference between the two power supplies is greater.

Current-limited latch

Systems for variable programming of non-volatile memory

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Fremont, CA, United States of America

Chi-Ming Wang