Taiwan Semiconductor Manufacturing Comp. Ltd.

Pegatron Corporation

Chi-Ming Tsai

Chi-Ta Lu

Liang-Guang Chen

Fu-Ming Huang

Han-Hsin Kuo

Ming-Che Ho

Jia-Guei Jou

Chih-Chung Huang

Chung-Shi Liu

Hao-Yi Tsai

Chih-Wei Lin

Yen-Liang Lin

Ming Hung Tseng

Wen-Hao Cheng

Tzu-Sung Huang

Ming-Ho Tsai

Yin-Chuan Chen

Ching-Hung Lai

Chung-Chi Ko

Chih-Chiang Tu

Neng-Jye Yang

Peng-Ren Chen

Jyun-Hong Chen

Chin-Min Huang

Yu-Nu Hsu

Wei-Chung Hu

Chun-Chen Liu

Hui-Chi Huang

He Hui Peng

Yu-Ting Yen

Sheng-Wen Huang

Ming-Te Lin

Yihung Lin

Wei-Lin Chu

Hsin-Lun Tseng

Chia-Hui Liao

Chen-Hua Douglas Yu

Ru-Gun Liu

Hung-Jui Kuo

Ming-Chung Liang

Chun-Nan Chen

Chung-Hung Lin

Shich-Chang Suen

Shuo-Yen Chou

Tzung-Hui Lee

Kuan-Chi Chen

Huang-Ming Wu

Shin-Huang Chen

Jiun-Hao Lin

Yen-Tung Hu

Ya-Hsuan Wu

Shiuan-Li Lin

He-Hui Peng

Yi-Chiuan Luo

Hao-Jen Liao

Cun-Hong Deng

A buffer module including a base, a buffer element and an elastic element is provided. The base has a groove. The buffer element includes a spherical body movably disposed in the groove. The elastic element is disposed between a bottom surface of the groove and the spherical body.

Buffer module and electronic device using the same

A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.

Semiconductor device

A method for forming a photomask includes following operations. A first photomask is received. The first photomask includes a first pattern and a first scattering bar. The first photomask is used to remove a first portion of a target layer to form a first opening and a second opening. The first opening corresponds to the first pattern, and the second opening corresponds to the first scattering bar. A second photomask is received. The second photomask includes a second pattern. The second photomask is used to remove a second portion of the target layer to form a third opening. The third opening corresponds to the second pattern. The second opening is widened to form the third opening using the second photomask.

Photomask and method for manufacturing photomask and semiconductor structure thereof

A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a second conductive line disposed adjacent to the first conductive line, surrounded by the dielectric layer and extended parallel to the first conductive line; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via substantially parallel to the first surface of the substrate, wherein the cross section of the conductive via is at least partially protruded from the first conductive line towards the second conductive line. Further, a method of manufacturing the semiconductor structure is also disclosed.

Semiconductor structure and manufacturing method thereof

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Integrated circuit package and method

A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

Critical dimension uniformity

A method for manufacturing a semiconductor device is provided. The method includes the following operations. A first layout including a plurality of first features is provided. A modified second layout is determined. The modified second layout includes a plurality of modified features separated from each other, and each of the plurality of modified features respectively overlaps each of the plurality of first features. The modified second layout is outputted to a photomask.

Method for manufacturing semiconductor device

A method includes: receiving a design layout comprising a feature extending in a peripheral region and a central region of the design layout; determining compensation values associated with a pellicle assembly and the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout according to the compensation values. The modifying of the shape of the feature according to the compensation values includes: partitioning the peripheral region into compensation zones, wherein the feature includes first portions disposed within the respective compensation zones and a second portion disposed within the central region; and reducing line widths of the first portions of the feature according to the compensation values associated with the respective compensation zones while keep the second portion of the feature uncompensated.

Method and system for reducing layout distortion due to exposure non-uniformity

A positioning fixture including a shielding member and a driving member is provided. The shielding member includes a sliding part slidably connected to a functional module, a guiding part, and a shielding part. The sliding part and the shielding part respectively extend from two opposite ends of the guiding part. The driving member is movably disposed on the functional module corresponding to the shielding member. The driving member includes a base part, a driving part that contacts the guiding part, and a pillar part, which protrudes from the base part and is adapted to pass through the guiding groove. When the functional module is positioned on the circuit board, the base part of the driving member is pushed by the electronic component, and the guiding part is pushed by the driving part, so that the shielding member slides and the shielding part shields a screw hole of the circuit board.

Positioning fixture

A method includes providing a first design layout including cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; training a model based on a layout-dependent parameter of a second design layout; and updating a second cell based on the data set and the model to provide a second updated cell. The model includes an input layer, a hidden layer and an output layer. Training the model includes obtaining converged values of nodes of the hidden layer. Obtaining converged values of nodes of the hidden layer includes providing information on edge segments before and after lithography enhancement to the input layer and the output layer, respectively, until values of nodes of the hidden layer attains convergence in terms of a cost function.

Method and system for layout enhancement based on inter-cell correlation

A method for forming a photomask is provided. The method includes: receiving an initial layout, the initial layout comprising a first pattern and a second pattern; decomposing the initial layout into a first layout including the first pattern and a second layout including the second pattern; inserting a third pattern into the first layout; overlapping the first layout including the first pattern and the third pattern to the second layout including the second pattern; increasing a width of the third pattern in the first layout overlapping the second pattern in the second layout to form a fourth pattern in the first layout; and outputting the first layout comprising the first pattern, the third pattern and the fourth pattern into a first photomask.

Growing community of inventors

Taipei, Taiwan

Chi-Ming Tsai