Macronix International Co., Ltd.

Nuvoton Technology Corporation

Powerchip Semiconductor Manufacturing Corporation

Analog Integrations Corporation

Canyon Semiconductor Inc.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Mediatek Corporation

Phoenix Precision Technology Corporation

Chi-Ming Chen

Pi-Fen Chen

Chun-Lin Lu

Shou-Zen Chang

Jing-Chyi Wang

Chung-Yi Yu

Po-Chun Liu

Chien-Hung Lin

Chien-Chung Hung

Pei-Kuei Tsung

Young-Shying Chen

Chang-Ting Chen

Min-Chang Ching

Chen-Hao Chiang

Lien-Chang Wang

Ying-Tsung Chu

Chung-Chieh Hsu

ShengJe Hung

Meng-Hsuan Cheng

Ding-Yu Wei

A semiconductor package structure includes a control unit and a memory unit. The control unit includes a first wafer and a second wafer that are vertically stacked. The memory unit is disposed on the second wafer of the control unit. The memory unit includes multiple third wafers and a fourth wafer that are stacked vertically. The memory unit overlaps the control unit in a normal direction of the semiconductor package structure. In addition, a manufacturing method of the semiconductor package structure is provided.

Semiconductor package structure and manufacturing method thereof

A high electron mobility transistor (HEMT) includes a substrate; and a first semiconductor layer over the substrate. The HEMT further includes a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a band gap discontinuity with the first semiconductor layer, and at least one of the first semiconductor layer or the second semiconductor layer comprises indium. The HEMT further includes a top layer over the second semiconductor layer. The HEMT further includes a gate electrode over the top layer. The HEMT further includes a source and a drain on opposite sides of the gate electrode, wherein the top layer extends continuously from below the source, below the gate electrode, and to below the drain.

High electron mobility transistor (HEMT) having an indium-containing layer and method of manufacturing the same

The invention provides a semiconductor bonding structure, the semiconductor bonding structure includes a first chip and a second chip which are bonded with each other, the first chip has a first bonding pad and the second bonding pad contacted and electrically connected to each other on a bonding interface, the first bonding pad and the second bonding pad are made of copper, and a heterogeneous contact combination in the first chip, the heterogeneous contact combination comprises a contact stack structure of a copper element, a tungsten element and an aluminum element, the tungsten element is located between the copper element and the aluminum element.

Semiconductor bonding structure

A processing unit performs multiply-and-accumulate (MAC) operations on asymmetrically quantized data. The processing unit includes a MAC hardware unit to perform the MAC operations on a first data sequence and a second data sequence to generate an asymmetric MAC output. Both the first data sequence and the second data sequence are asymmetrically quantized. The processing unit further includes an accumulator hardware unit to accumulate the first data sequence concurrently with the MAC operations to generate an accumulated output. The processing unit further includes a multiply-and-add (MAD) hardware unit to multiply the accumulated output with a second offset to generate a multiplication output, and to add the multiplication output, the asymmetric MAC output and a pre-computed value calculated before runtime to generate a final output. The second offset indicates an amount of asymmetry of the second data sequence with respect to zero.

Asymmetric quantization of multiple-and-accumulate operations in deep learning processing

An electronic device includes a voltage converter configured to provide an output having an output voltage value and an output current value. The electronic device also includes a handshake control unit a handshake control unit, coupled to the voltage converter, configured to perform a handshake process for a charging voltage value and receive a matching result of the handshake process. The electronic device further includes a matching management unit, coupled to the handshake control unit, configured to send a first request for resuming matching to the handshake control unit in response to the matching result as being failed.

Electronic device for charging and charging method thereof

An electronic device includes an input power detection unit, a transmission control unit and a converter. The input power detection unit is configured to determine an input voltage value and an input current value of an input power. In response to the input power, the transmission control unit is configured to determine a first voltage value and a first current value associated with another electronic device via a handshake process. The voltage converter is configured to convert the input power into a first power required by the another electronic device.

Apparatus for input power detection and method thereof

A bus interface includes a chip select terminal, a first transmission bus terminal, a second transmission bus terminal, and a clock control device. The chip select terminal transmits a chip select signal to start the data transmission. When the data transmission starts, the first transmission bus terminal sends data to the second device, and the second transmission bus terminal sends the data from the second device to the first device. The clock control device includes a frequency processing unit and a transmission clock generating unit. The frequency processing unit outputs a clock control signal when a frequency to set value changes. The transmission clock generating unit receives the clock control signal and generates a transmission clock in accordance with the frequency setting value.

Integrated circuit and clock frequency control method of integrated circuit

A driving circuit includes a switch, a detecting unit, a current supply unit, and an energy storage unit. The current supply unit is used for providing a driving current for at least one series of light emitting diodes. The detecting unit is used for comparing a voltage of a first terminal of the detecting unit with a reference voltage to generate a switch control signal. When the switch is turned on according the switch control signal, a first voltage drives the series of light emitting diodes through the switch and the energy storage unit is charged according a charge current. When the switch is turned off according the switch control signal, the energy storage unit drives the series of light emitting diodes according to a discharge current.

Driving circuit capable of enhancing energy conversion efficiency and driving method thereof

A driving circuit includes a switch, a detecting unit, and a current supply unit. A first terminal of the switch is used for coupling to a first terminal of a first LED group of a plurality of LED groups and receiving a first voltage, and a third terminal of the switch is used for coupling to a first terminal of a last LED group of the plurality of LED groups. The detecting unit is used for outputting a switch control signal to a second terminal of the switch for controlling turning-on and turning-off of the switch. The current supply unit has a plurality of input current terminals, and a ground terminal coupled to ground, where each input current terminal of the plurality of input current terminals is used for coupling to a second terminal of a corresponding LED group of the plurality of LED groups.

A data transmission system is provided. The data transmission system includes a serial peripheral interface (SPI) and a programmable controller. The SPI is coupled between a first device and at least one second device. The programmable controller controls the SPI to switch between a single port data transmission mode and a multi-port data transmission mode. When there are more than one second device coupled to the SPI, the SPI is switched to the multi-port data transmission mode so as to perform multi-port data transmission between the first device and the second devices. At this time, the first device concurrently transmits data to each of the second devices via a first transmission bus terminal, and concurrently receives data from each of the second devices via a second transmission bus terminal.

Data transmission system and a programmable SPI controller

A magnetic memory array. A first bit line provides a first writing magnetic field to a magnetic memory cell. A second bit line provides a second writing magnetic field to a reference magnetic memory cell. A word line provides a third writing magnetic field to the magnetic memory cell and a fourth writing magnetic field to the reference magnetic memory cell. The third writing magnetic field exceeds the fourth writing magnetic field.

Magnetic memory arrays

A memory device includes an array of storage cells, multiple words lines, where each word line corresponds to a row in the array of storage cells, and multiple bit lines, where each bit line corresponds to a column in the array of storage cells. The device further includes a row decoder attached to the multiple word lines. The row decoder is operable to assert and to de-assert individual word lines. Each of the word lines has a head portion adjacent to where the word line is attached to the row decoder. The memory device supports a column decode sequence for accessing multiple storage cells within a row of the array. The column decode sequence both commences and terminates at or near the head portion of the word line corresponding to the row.

Memory device with rapid word line switch

A method of embedding a semiconductor element in a carrier and an embedded structure thereof are proposed. First, a carrier having a hole is provided and an auxiliary material is attached to a side of the carrier. A semiconductor element is placed in the hole of the carrier. Then, a medium material and glue are applied in order in the hole to firmly position the semiconductor element in the hole of the carrier via the glue. Finally, the auxiliary material and the medium material are removed to form a structure with the semiconductor element being embedded in the carrier, thereby eliminating the drawbacks encountered in packing the semiconductor element in the prior art.

Method of embedding semiconductor element in carrier and embedded structure thereof

The invention provides a peak detector having input signal triggering control and low frequency energy attenuation capability. The peak detector includes a charging unit and a discharging unit. By being triggered by a peak value detected in a received input signal by comparing voltage potential levels of the output signal of the peak detector and the received signal, the charging unit charges an electrical charge storage unit, for example, a capacitor, connected to the output terminal of the peak detector for a pre-determined charge duration in accordance with a charge pulse being in a logic high. After the pre-determined charge duration of charging operation, before being triggered by a next peak value of the received input signal, the discharging unit discharges the electrical charge storage unit for a pre-determined discharge duration in accordance with a discharge pulse being in a logic high or in accordance with a plurality of discharge pulses, which is determined by design desired.

Peak detector and detecting method thereof

In the present invention, a transmission line length estimation circuit with continuous feedback equalizer is provided. The transmission line length estimation circuit comprises a DC bias circuit and a peak detector circuit to generate a DC voltage according to a different cable length. An equalizer core circuit is for receiving the first signal and generating a second signal. A peak detector circuit is used for the first signal and the second signal. A transmission line length detector circuit is coupled to the peak detector circuit and used for generating a plurality of first parameters for phase shift and amplitude losses according to the different cable length. An internal pattern calibration circuit is multiplexed to the first signal and used for generating a plurality of second parameters for calibration of close loop. A feedback control circuit is connected to the equalizer core circuit and used for continuously fine tuning of the equalizer core circuit according to the first parameters and the second parameters.

Growing community of inventors

Hsinchu, Taiwan

Chi-Ming Chen