Mediatek Corporation

Mediatek Incorporation

Chi-Ming Chang

Hong-Ching Chen

Hao-Yung Wang

Chih-Peng Chang

Jia-Hau Lin

Chin-Ling Hung

A wireless communication system comprises a plurality of antennas, a plurality of tuners, a plurality of receiver ends, a bus, and a processor. Each of the tuners is connected to one of the antennas and one of the receiver ends. Each of the receiver ends has a corresponding address. A common address code is assigned to the corresponding addresses of part of receiver ends during firmware loading. The processor transmits the firmware to the part of the receiver ends via the bus based on the common address code. The corresponding addresses of the part of the receiver ends are converted back into unique address codes after the firmware is loaded.

Wireless communication receiver, system, and method for loading firmware

A PLL system for generating an output signal according to a first reference signal is disclosed. The PLL system includes a clock generator to generate the output signal according to a phase difference between the first reference signal and the frequency-divided signal; and a phase-shift detector for detecting a position difference between the physical address and an updated logical address of the recording data to generate a phase adjusting signal. The PLL system also includes an adder for updating a detected logical address with a random value to output the updated logical address to the position difference detector; and a phase-controllable frequency divider for generating the frequency-divided signal and for receiving the phase adjusting signal to adjust the phase of the frequency-divided signal.

Phase locked loop for controlling a recording device and method thereof

A data slice signal generation method of an optical disk drive, which uses a disk including header areas and data areas of different materials, includes the following steps. First, a data slice signal is generated according to the RF signal read by the optical pickup head of the optical disk drive, and the data slice values, reflecting the central levels of the RF signal, of the data slice signal at the beginnings of the header area and data area are preset. Secondly, when the optical pickup head of the optical disk drive enters a header area or a data area, the data slice signal takes the preset data slice value of the header area or data area, respectively. Then, the data slice signal is adjusted to approach the central levels of the waves of the RF signal by one wave after another.

Data slice generation method and apparatus for optical disk drive

A protecting device installed in an optical storage system for protecting a plurality of physical identification data synchronous signals includes a synchronous pattern detecting device, a data synchronous signal insertion device for adding the amount of data synchronous signals to a first predetermined number, a counting/reloading device for sequentially counting the first predetermined number of data synchronous signals and an additional second predetermined number of data synchronous signals, a PID window generator for generating a plurality of protecting windows respectively corresponding to the plurality of physical identification data synchronous signals while the counting/reloading device is counting the second predetermined number of data synchronous signals, and a PID synchronous signal protection device for protecting the plurality of physical identification data synchronous signals according to the plurality of protecting windows.

Apparatus for PID address protection and method thereof

A phase locked loop (PLL) system for generating a reference clock to write recording data on an optical medium includes a clock generator generating the reference clock according to a phase difference between the reference signal and a first frequency-divided signal; a phase-shift detector generating a phase adjusting signal; and a phase-controllable frequency divider dividing the frequency of the reference clock to generate the first frequency-divided signal, and receiving the phase adjusting signal to adjust the phase of the first frequency-divided signal. The phase-shift detector includes an ADIP sync detector generating an ADIP synchronization signal synchronous to the ADIP units of the optical medium; a frequency divider dividing the reference clock to generate a second frequency-divided signal; and a phase difference detector detecting a phase difference between the second frequency-divided signal and the ADIP synchronization signal to generate the phase adjusting signal.

Phase locked loop for controlling an optical recording device and method thereof

The invention system adjusts a phase/frequency detecting device in a phase locked loop. The phase/frequency detecting device compares a target clock signal generated from the phase locked loop with a predetermined reference clock signal, and outputs a set of control signals to further control the target clock signal to synchronize with the reference clock signal. A reset module counts the set of control signals and outputs a set of reset signals when a predetermined reset condition is met. A switch module counts the set of reset signals and switches the phase/frequency detecting device between a normal mode and a glitch protection mode when a predetermined switch condition is met. When the phase/frequency detecting device is under the glitch protection mode, and the predetermined reset condition set by the reset module is met, the reset module outputs the set of reset signals and resets the phase/frequency detecting device.

System and method to reduce glitch disturbance for phase/frequency detecting device

A PLL system for generating an output signal according to a first reference signal is disclosed. The output signal is used as a reference clock to write recording data on an optical medium. The PLL system includes a clock generator for receiving the first reference signal and a first frequency-divided signal to generate the output signal according to a phase difference between the first reference signal and the first frequency-divided signal; a phase-shift detector for generating a phase adjusting signal; and a phase-controllable frequency divider for dividing the frequency of the output signal by a frequency dividing ratio to generate the first frequency-divided signal and for receiving the phase adjusting signal to adjust the phase of the first frequency-divided signal.

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Tao-Yuan Hsien, Taiwan

Chi-Ming Chang