United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Chi-Mao Hsu

Hsin-Fu Huang

Chin-Fu Lin

Tsun-Min Cheng

Min-Chuan Tsai

Kuo-Chih Lai

Pin-Hong Chen

Po-Jen Chuang

Nien-Ting Ho

Tsuo-Wen Lu

Chien-Hao Chen

Wei-Yu Chen

Chia-Ming Kuo

Fu-Jung Chuang

Yi-Wei Chen

Chih-Chieh Tsai

Shih-Fang Tzou

Tzu-Chieh Chen

Chun-Ling Lin

Li-Han Chen

Kun-Hsien Lin

Chun-Chieh Chiu

Chi-Yuan Sun

Shih-Min Chou

Ching-Yun Chang

Chien-Ting Lin

Yu-Ren Wang

Chun-Hsien Lin

Chun-Yuan Wu

Yen-Chen Chen

Chien-Ming Lai

Chia-Chang Hsu

Tsung-Hsun Wu

Chia Chang Hsu

Yang-Ju Lu

Wei-Ming Hsiao

Shih-Cheng Chen

Shu Min Huang

Guan-Wei Huang

Shih-Hao Liang

Yun-Tzu Chang

Kuan-Chun Lin

Ssu-I Fu

Shu-Yen Chan

Wei-Chuan Tsai

Kai-Jiun Chang

Yi-An Huang

Chun-Hung Chen

Tien-Chen Chan

Ger-Pin Lin

Chia-Chen Wu

Kuo-Chin Hung

Bor-Shyang Liao

Tzung-Ying Lee

Min-Chung Cheng

Huei-Ru Tsai

Ya-Hsueh Hsieh

Feng-Yi Chang

Fu-Che Lee

Li-Wei Feng

Shih-Hung Tsai

Po-Chao Tsao

Hsin-Yu Chen

Ying-Chiao Wang

Yi-Wen Chen

Wen-Tai Chiang

Ying-Tsung Chen

Hsiang-Chieh Yen

Min-Hsien Chen

En-Chiuan Liou

Chien-Li Kuo

Yu-Ping Wang

Chan-Lon Yang

Chien-Chung Huang

Kuan-Cheng Su

Chih-Wei Yang

Tzyy-Ming Cheng

Shui-Yen Lu

Che-Hua Hsu

Zhi-Cheng Lee

Yu-Ru Yang

Chia-Fu Hsu

Tsai-Yu Wen

Shin-Chi Chen

Ya-Huei Tsai

Chih-Yueh Li

Chia-Wei Wu

Ching-Li Yang

Yuan-Chi Pai

Tong-Jyun Huang

Yen-Tsai Yi

Jian-Cun Ke

Yao-Chang Wang

Tsung-Yin Hsieh

Yu-Ting Tseng

Sheng-Huei Dai

Tzung-Lin Li

Chi-Ju Lee

Ting-Pang Chung

Szu-Hao Lai

A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

Semiconductor device having contact plug connected to gate structure on PMOS region

A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

Method for forming a thin film resistor with improved thermal stability

A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

Semiconductor device and method for fabricating the same

A semiconductor device includes a gate structure on a substrate, a first spacer on sidewalls of gate structure, a second spacer on sidewalls of the first spacer, a polymer block adjacent to the first spacer and on a corner between the gate structure and the substrate, an interfacial layer under the polymer block, and a source/drain region adjacent to two sides of the first spacer. Preferably, the polymer block is surrounded by the first spacer, the interfacial layer, and the second spacer.

The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Storage node contact structure of a memory device

A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a polymer block on a corner between the gate structure and the substrate; performing a cleaning process; performing an oxidation process by injecting oxygen gas under 750&#xb0; C. to form a first seal layer on sidewalls of the gate structure; and forming a source/drain region adjacent to two sides of the gate structure.

A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.

Bit line utilized in DRAM

A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.

Semiconductor structure for preventing row hammering issue in DRAM cell and method for manufacturing the same

A semiconductor device includes a substrate having a NMOS region and a PMOS region; a gate structure extending along a first direction from the NMOS region to the PMOS region on the substrate; and a first contact plug landing directly on the gate structure closer to the PMOS region from a boundary separating the NMOS region and the PMOS region. Preferably, the semiconductor device further includes a first source/drain region extending along a second direction adjacent to two sides of the gate structure on the NMOS region and a second source/drain region extending along the second direction adjacent to two sides of the gate structure on the PMOS region.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

Method for fabricating semiconductor device

Growing community of inventors

Tainan, Taiwan

Chi-Mao Hsu